V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

16.5.1. TX PMA Parameters

Note: For more information about PLLs in Cyclone V devices, refer to the Cyclone V PLLs section in Clock Networks and PLLs in Cyclone V Devices.
Table 298.  TX PMA Parameters

Parameter

Range

Description

Enable TX PLL dynamic reconfiguration

On/Off

When you turn this option On, you can dynamically reconfigure the PLL. This option is also required to simulate TX PLL reconfiguration. If you turn this option On, the Intel® Quartus® Prime Fitter prevents PLL merging by default; however, you can specify merging using the XCVR_TX_PLL_RECONFIG_GROUP QSF assignment.

Use external TX PLL

On/Off

When you turn this option On, the Native PHY does not include TX PLLs. Instead, the Native PHY includes a input clock port for connection to the fast clock from an external PLL, ext_pll_clk[<p>-1:0] that you can connect to external PLLs. Use feature when need to perform TX PLL switching between fractional PLL and a CMU PLL.

Number of TX PLLs

1–4

Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates. If your design does not require transceiver TX PLL dynamic reconfiguration, set this value to 1. The number of actual physical PLLs that are implemented depends on the selected clock network. Each channel can dynamically select between n PLLs, where n is the number of PLLs specified for this parameter.

Note: Refer to Transceiver Clocking in Cyclone V Devices chapter for more details.

Main TX PLL logical index

0–3

Specifies the index of the TX PLL used in the initial configuration.

Number of TX PLL reference clocks

1–5

Specifies the total number of reference clocks that are used by all of the PLLs.

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