V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

3.3. 10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices

Because the 10GBASE-R PHY is implemented in hard logic it uses less than 1% of the available ALMs, memory, primary and secondary logic registers. The following table lists the typical expected device resource utilization for duplex channels using the current version of the Intel® Quartus® Prime software targeting a Stratix IV GT device. The numbers of combinational ALUTs, logic registers, and memory bits are rounded to the nearest 100.

Table 8.  10GBASE-R PHY Performance and Resource Utilization—Stratix IV GT Device
Channels Combinational ALUTs Logic Registers (Bits) Memory Bits
1 5200 4100 4700
4 15600 1300 18800
10 38100 32100 47500