3.3. 10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices
Because the 10GBASE-R PHY is implemented in hard logic it uses less than 1% of the available ALMs, memory, primary and secondary logic registers. The following table lists the typical expected device resource utilization for duplex channels using the current version of the Intel® Quartus® Prime software targeting a Stratix IV GT device. The numbers of combinational ALUTs, logic registers, and memory bits are rounded to the nearest 100.
|Channels||Combinational ALUTs||Logic Registers (Bits)||Memory Bits|
Did you find the information on this page useful?