V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

17.26.1. Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration

Complete the following reads and writes to the Streamer module to enable the PRBS verifier in the Standard PCS:

  1. Read the Streamer Module control and status register busy bit (7’h3A, bit[8]) until it is clear.
  2. Write the Streamer Module logical channel number to the Streamer logical channel number register at address 0x38.
  3. Set the Streamer Module control and status register Mode bits (7’h3A, bits[3:2]) to 1.
  4. Determine the PRBS pattern from the table above and note the corresponding word aligner size and word aligner pattern. The word aligner size and word aligner pattern are used in the next two steps. For example, using a 16-bit PCS/PMA width and a PRBS-23 pattern the corresponding word aligner size is 3’b101 and word aligner pattern is 0x00007FFFFF.
  5. Perform a read-modify-write to the Word Aligner Size field (offset 0xA1, bits[10:8]) to change the word aligner size.
  6. Because the word aligner pattern is specified in three separate register fields, to change the word aligner pattern, you must perform read-modify-writes to the following three register fields:
    1. Word Aligner Pattern, bits [39:32] (offset 0xA1, bits [7:0] )
    2. Word Aligner Pattern, bits [31:16] (offset 0xA2, bits [15:0])
    3. Word Aligner Pattern, bits [15:0] (offset 0xA2, bits [15:0])
  7. To enable the PRBS verifier, perform the following three read-modify-write operations to set the values of these bits to 0:
    1. Sync badcg, (offset 0xA1, bits[15:14])
    2. Enable Comma Detect, (offset 0xA1, bit[13])
    3. Enable Polarity, (offset, 0xA1, bit[11])
  8. Now, you must set the proper value for the Sync State Machine Disable bit.
    • If your PCS/PMA interface width is 8 or 10 bits, perform a read-modify-write with a value of 1'b1 to Sync State Machine Disable (offset 0xA4, bit[15]).
    • If your PCS/PMA interface width is 16 or 20 bits, perform a read-modify-write with a value of 1'b0 to Sync State Machine Disable (offset 0xA4, bit[15]).
  9. To complete the necessary programming,
    1. Perform read-modify-writes to set the following bits to 0:
      • Auto Byte Align Disable (offset 0xA6, bit[5])
      • DW Sync State Machine Enable (offset 0xB8, bit[13])
      • Deterministic Latency State Machine Enable (offset 0xB9, bit[11])
      • Clock Power Down RX (offset 0xBA, bit[11])
    2. Perform read-modify-writes to set the following bits to 1:
      • PRBS RX Enable (offset 0xA0, bit[5])
  10. Assert the channel reset.

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