17.18. Transceiver Reconfiguration Controller Streamer Module Registers
The Streamer module defines the following two modes for channel and PLL reconfiguration:
- Mode 0—MIF. Uses a memory initialization file (.mif) to reconfigure settings.
- Mode 1—Direct Write. Uses a series of Avalon-MM writes on the reconfiguration management interface to change settings.
|PHY Addr||Bits||R/W||Register Name||Description|
|7’h38||[9:0]||RW||logical channel number||The logical channel number. Must be specified when performing dynamic updates. The Transceiver Reconfiguration Controller maps the logical address to the physical address.|
|7’h3A||||R||control and status||
Error. When asserted, indicates an error. This bit is asserted if any of the following conditions occur:
|||R||Busy. When asserted, indicates that a reconfiguration operation is in progress.|
Mode. The following encodings are defined:
|||W||Read. Writing a 1 to this bit triggers a read operation. This bit is self clearing.|
|||W||Write. Writing a 1 to this bit triggers a write operation. This bit is self clearing.|
|7’h3B||[15:0]||RW||streamer offset||When the MIF Mode = 2’b00, the offset register specifies a an internal MIF Streamer register. This register cannot be set to a value greater than 0x2 when control and status register is set to MIF mode. You must ensure that appropriate values are set for this register, when you switch between MIF mode and Direct Write mode. Refer to Table 341 for definitions of these registers. WhenMIF Mode = 2’b01, offset register specifies register in the transceiver.|
|7’h3C||[31:0]||RW||data||When the MIF Mode = 2’b00, the data register stores read or write data for indirect access to the location specified in the offset register. When MIF Mode = 2’b01, data holds an update for transceiver to be dynamically reconfigured.|
|0x0||[31:0]||RW||MIF base address||Specifies the MIF base address.|
|0x1||||RW||Clear error status||
Writing a 1 to this bit clears any error currently recorded in an indirect register. This register self clears.
Any error detected in the error registers prevents MIF streaming. If an error occurs, you must clear the error register before restarting the Streamer.
|||RW||MIF address mode||When set to 0, the streamer uses byte addresses. When set to 1, the streamer uses word addresses (16 bits).|
|||RW||Start MIF stream||Writing a 1 to this register, triggers a MIF streaming operation. This register self clears.|
|0x2||||RO||MIF or Channel mismatch||
When asserted, indicates the MIF type specified is incorrect. For example, the logical channel is duplex, but the MIF type specifies an RX only channel. The following 5 MIF types are defined:
|||RO||PLL reconfiguration IP error||When asserted, indicates that an error occurred changing a refclk or clock generation block setting.|
|||RO||MIF opcode error||When asserted, indicates that an undefined opcode ID was specified in the .mif file, or the first entry in the .mif file was not a start of MIF opcode.|
|||RO||Invalid register access||When asserted, indicates that the offset register address specified is out of range.|
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