V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

14.5.1. TX PMA Parameters

This section describes the TX PMA options you can specify.
Note: For more information about PLLs in Arria V devices, refer to the Arria V PLLs section in Clock Networks and PLLs in Arria V Devices.
Table 228.  TX PMA Parameters




Enable TX PLL dynamic reconfiguration


When you turn this option On, you can dynamically reconfigure the PLL. This option is also required to simulate TX PLL reconfiguration. If you turn this option On, the Intel® Quartus® Prime Fitter prevents PLL merging by default; however, you can specify merging using the XCVR_TX_PLL_RECONFIG_GROUP QSF assignment.

Use external TX PLL


When you turn this option On, the Native PHY does not automatically instantiate a TX PLL. Instead, you must instantiate an external PLL and connect it to the ext_pll_clk[<p> -1 : 0] port of the Arria V Native PHY.

Use the Arria V Transceiver PLL IP Core to instantiate a CMU PLL. Use Altera Phase-Locked Loop (ALTERA_ PLL) Megafunction to instantiate a fractional PLL.

Number of TX PLLs


Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates. If your design does not require transceiver TX PLL dynamic reconfiguration, set this value to 1. The number of actual physical PLLs that are implemented depends on the selected clock network. Each channel can dynamically select between n PLLs, where n is the number of PLLs specified for this parameter.

Note: Refer to Transceiver Clocking in Arria V Devices chapter for more details.

Main TX PLL logical index


Specifies the index of the TX PLL used in the initial configuration.

Number of TX PLL reference clocks


Specifies the total number of reference clocks that are used by all the PLLs.

Did you find the information on this page useful?

Characters remaining:

Feedback Message