1.7. Running a Simulation Testbench
When you generate your transceiver PHY IP core, the Intel® Quartus® Prime software generates the HDL files that define your parameterized IP core. In addition, the Intel® Quartus® Prime software generates an example Tcl script to compile and simulate your design in ModelSim.
The following table describes the key files and directories for the parameterized transceiver PHY IP core and the simulation environment which are in clear text.
|<project_dir>||The top-level project directory.|
|<instance_name> .v or .vhd||The top-level design file.|
|<instance_name> .qip||A list of all files necessary for Intel® Quartus® Prime compilation.|
|<instance_name> .bsf||A Block Symbol File (.bsf) for your transceiver PHY.|
|<project_dir>/<instance_name>/||The directory that stores the HDL files that define the protocol-specific PHY IP core. These files are used for synthesis.|
|sv_xcvr_native.sv||Defines the transceiver. It includes instantiations of the PCS and PMA modules and Avalon-MM PHY management interface.|
|stratixv_hssi_ <module_name> _rbc. sv||These files perform rule based checking for the module specified. For example, if the PLL type, data rate, and FPGA fabric transceiver interface width are not compatible, the checker reports an error.|
|altera_wait_generate.v||Generates waitrequest for protocol-specific transceiver PHY IP core that includes backpressure.|
|alt_reset_ctrl_tgx_cdrauto.sv||Includes the reset controller logic.|
|<instance_name> _phy_assignments.qip||Includes an example of the PLL_TYPE assignment statement required to specify the PLL type for each PLL in the design. The available types are clock multiplier unit (CMU) and auxiliary transmit (ATX).|
|<project_dir>/<instance_name> _sim/ altera_xcvr_ <PHY_IP_name>/||The simulation directory.|
|<project_dir>/<instance_name>_sim/ aldec||Simulation files for Riviera-PRO simulation tools.|
|<project_dir>/<instance_name>_sim/ cadence||Simulation files for Cadence simulation tools.|
|<project_dir>/<instance_name>_sim/ mentor||Simulation files for Mentor simulation tools.|
|<project_dir>/<instance_name>_sim/ synopsys||Simulation files for Synopsys simulation tools.|
The Verilog and VHDL transceiver PHY IP cores have been tested with the following simulators:
- ModelSim SE
- Synopsys VCS MX
- Cadence NCSim
If you select VHDL for your transceiver PHY, only the wrapper generated by the Intel® Quartus® Prime software is in VHDL. All the underlying files are written in Verilog or System Verilog.
For more information about simulating with ModelSim, refer to the Mentor Graphics ModelSim and QuestaSim Support chapter of the Intel® Quartus® Prime Handbook.
The transceiver PHY IP cores do not support the NativeLink feature in the Intel® Quartus® Prime software.
Generating Custom Simulation Scripts for Multiple Transceiver PHYs with ip-make-simscript
Use the ip-make-simscript utility to generate simulation command scripts for multiple transceiver PHYs or Qsys systems. Specify all Simulation Package Descriptor files (.spd). The .spd files list the required simulation files for the corresponding IP core. The MegaWizard Plug-In Manager and Qsys generate the .spd files.
When you specify multiple .spd files, the ip-make-simscript utility generates a single simulation script containing all required simulation information. The default value of TOP_LEVEL_NAME is the TOP_LEVEL_NAME defined in the IP core or Qsys .spd file. If this is not the top-level instance in your design, specify the top-level instance of your testbench or design.
You can set appropriate variables in the script or edit the variable assignments directly in the script. If the simulation script is a Tcl file that can be sourced in the simulator, set the variables before sourcing the script. If the simulation script is a shell script, pass in the variables as command-line arguments to shell script.
To run ip-make-simscript , type the following at the command prompt:
<ACDS installation path>\quartus\sopc_builder\bin\ip-make-simscript
Describes the list of compiled files and memory model hierarchy. If your design includes multiple IP cores or Qsys systems that include .spd files, use this option for each file. For example:ip-make-simscript --spd=ip1.spd --spd=ip2.spd
Directory path specifying the location of output files. If unspecified, the default setting is the directory from which ip-make-simscript is run.
Compiles all design files to the default work library. Use this option only if you encounter problems managing your simulation with multiple libraries.
|--use-relative-paths||Uses relative paths whenever possible||Optional|
To learn about all options for the ip-make-simscript , type the following at the command prompt:
<ACDS installation path>\quartus\sopc_builder\bin\ip-make-simscript --help
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