V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

16.6.2. Byte Ordering Block Parameters

The RX byte ordering block realigns the data coming from the byte deserializer. This block is necessary when the PCS to FPGA fabric interface width is greater than the PCS datapath.

Because the timing of the RX PCS reset logic is indeterminate, the byte ordering at the output of the byte deserializer may or may not match the original byte ordering of the transmitted data.

Note: For more information refer to the Byte Ordering section in the Transceiver Architecture in Cyclone V Devices.
Table 303.  Byte Ordering Block Parameters   




Enable RX byte ordering


When you turn this option On, the PCS includes the byte ordering block.

Byte ordering control mode



Specifies the control mode for the byte ordering block. The following modes are available:

  • Manual: Allows you to control the byte ordering block
  • Auto: The word aligner automatically controls the byte ordering block once word alignment is achieved.

Byte ordering pattern width


Shows width of the pattern that you must specify. This width depends upon the PCS width and whether or not 8B/10B encoding is used as follows:


8, 16,32

10, 20, 40

8, 16, 32





Pad Pattern

8 bits

10 bits

9 bits

Byte ordering symbol count


Specifies the number of symbols the word aligner should search for. When the PMA is 16 or 20 bits wide, the byte ordering block can optionally search for 1 or 2 symbols.

Byte order pattern (hex)

User-specified 8-10 bit pattern

Specifies the search pattern for the byte ordering block.

Byte order pad value (hex)

User–specified 8-10 bit pattern

Specifies the pad pattern that is inserted by the byte ordering block. This value is inserted when the byte order pattern is recognized.

The byte ordering pattern should occupy the least significant byte (LSB) of the parallel TX data. If the byte ordering block identifies the programmed byte ordering pattern in the most significant byte (MSB) of the byte-deserialized data, it inserts the appropriate number of user-specified pad bytes to push the byte ordering pattern to the LSB position, restoring proper byte ordering.

Enable rx_std_byteorder_ena port


Enables the optional rx_std_byte_order_ena control input port. When this signal is asserted, the byte ordering block initiates a byte ordering operation if the Byte ordering control mode is set to manual. Once byte ordering has occurred, you must deassert and reassert this signal to perform another byte ordering operation. This signal is an synchronous input signal; however, it must be asserted for at least 1 cycle of rx_std_clkout.

Enable rx_std_byteorder_flag port


Enables the optional rx_std_byteorder_flag status output port. When asserted, indicates that the byte ordering block has performed a byte order operation. This signal is asserted on the clock cycle in which byte ordering occurred. This signal is synchronous to the rx_std_clkout clock.