V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

13.4.1. General Parameters for Stratix V Native PHY

This section describes the datapath parameters in the General Options tab for the Stratix V native PHY.

Table 181.  General and Datapath OptionsThe following table lists the parameters available on the General Options tab. Note that you can enable the Standard PCS, the 10G PCS, or both if you intend to reconfigure between the two available PCS datapaths.
Name Range Description
Device speed grade fastest - 3_H3 Specifies the speed grade.
Message level for rule violations

error

warning

When you select the error message level, the Intel® Quartus® Prime rules checker reports an error if you specify incompatible parameters. If you select the warning message level, the Intel® Quartus® Prime rules checker reports a warning instead of an error.
Datapath Options
Enable TX datapath On/Off When you turn this option On, the core includes the TX datapath.
Enable RX datapath On/Off When you turn this option On, the core includes the RX datapath.
Enable Standard PCS On/Off When you turn this option On, the core includes the Standard PCS . You can enable both the Standard and 10G PCS if you plan to dynamically reconfigure the Native PHY.
Enable 10G PCS On/Off When you turn this option On, the core includes the 10G PCS. You can enable both the Standard and 10G PCS if you plan to dynamically reconfigure the Native PHY.
Initial PCS datapath selection Enable Standard PCS

Enable 10G PCS

Specifies the active datapath when you enable both the Standard PCS and 10G PCS.
Number of data channels Device Dependent Specifies the total number of data channels in each direction. From 1-32 channels are supported.
Bonding mode

Non-bonded or x1

×6/×N

fb_compensation

In Non-bonded or x1 mode, each channel is paired with a PLL. If one PLL drives multiple channels, PLL merging is required. During compilation, the Intel® Quartus® Prime Fitter, merges all the PLLs that meet PLL merging requirements. Refer to Merging TX PLLs In Multiple Transceiver PHY Instances to observe PLL merging rules.

When you select ×6/×N Bonding Mode, the Intel® Quartus® Prime software uses a single TX PLL to generate the clock for up to 6 channels in a single transceiver bank. If the channels used cross a transceiver bank boundary, the Intel® Quartus® Prime software uses the ×N clock lines to route the same clock source to the channels.

Bonded channels do not support dynamic reconfiguration of the transceiver.

Select fb_compensation (feedback compensation) to use the same clock source for multiple channels across different transceiver banks to reduce clock skew. For more information about bonding, refer to "Bonded Channel Configurations Using the PLL Feedback Compensation Path" in volume 2 of the Stratix V Device Handbook.

Enable simplified data interface On/Off When you turn this option On, the Native PHY presents only the relevant data bits. When you turn this option Off, the Native PHY presents the full raw interface to the fabric. If you plan to dynamically reconfigure the Native PHY, you must turn this option Off and you need to understand the mapping of data to the FPGA fabric. Refer to Table 189 for more information. When you turn this option On , the Native PHY presents an interface that includes only the data necessary for the single configuration specified.

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