V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

11.4. General Options Parameters

The following table lists the settings available on General Options tab:

Table 150.  Low Latency PHY General Options

Name

Value

Description

Device family

Stratix V

This IP core is only available for Stratix V devices.

Datapath type

Standard

10G

GT

The Low Latency PHY IP Core is part of a Standard, 10G, or GT datapath. In most cases the FPGA fabric transceiver interface width determines the bandwidth of the datapath; however, when the FPGA fabric transceiver interface width is 32 or 40 bits, you have the option of using either the Standard datapath which is the default mode, or changing to the 10G datapath by selecting this option. Refer to Table 151 Datapath Width Support for a comprehensive list of datapath support.

Mode of operation

Duplex

RX

TX

Specifies the mode of operation as Duplex, RX, or TX mode.

Number of lanes

1-32

Specifies the total number of lanes in each direction. Stratix V devices include up to 32 GX channels (Standard or 10G) and up to 4 GT channels. You must instantiate each GT channel in a separate Low Latency PHY IP Core instance. You cannot specify both GX and GT channels within the same instance.

Enable lane bonding

On/Off

When enabled, the PMA uses the same clock source for up to 6 channels in a transceiver bank, reducing clock skew.

Turn this option Off if you are using multiple TX PLLs in a single Low Latency PHY IP Core instance.

Bonding mode

×N

fb_compensation

Select ×N to use the same clock source for up to 6 channels in a single transceiver bank, resulting in reduced clock skew. You must use contiguous channels when you select ×N bonding. In addition, you must place logical channel 0 in either physical channel 1 or 4. Physical channels 1 and 4 are indirect drivers of the ×N clock network.

Select fb_compensation (feedback compensation) to use the same clock source for multiple channels across different transceiver banks to reduce clock skew.

For more information about bonding, refer to “Bonded Channel Configurations Using the PLL Feedback Compensation Path” in Transceiver Clocking in Stratix V Devices in volume 2 of the Stratix V Device Handbook.

FPGA fabric transceiver interface width

8, 10, 16, 20, 32, 40, 50, 64, 66, 128

This option indicates the parallel data fabric transceiver interface width. GT datapath supports a single width of 128 bits. Refer to Table 151 Datapath Width Support for the supported interface widths of the Standard and 10G datapaths.

PCS PMA interface width

8, 10, 16, 20, 30, 32, 64

The PCS-PMA interface width depends on the FPGA fabric transceiver interface width and the Datapath type. Refer to Datapath Width Support for the supported interface widths of the Standard and 10G datapaths.

PLL type

CMU

ATX

The CMU PLL is available for the Standard and 10G datapaths. The ATX PLL is available for the Standard, 10G, and GT datapaths. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of data rates and reference clock frequencies. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does.

An informational message displays in the message panel if the PLL type that you select is not available at the frequency specified.

Data rate

Device dependent

Specifies the data rate in Mbps. Refer to Stratix V Device Datasheet for the data rate ranges of datapath.

Base data rate

1 × Data rate

2 × Data rate

4 × Data rate

Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission. By selecting an appropriate base data rate, you can change data rates by changing the divider used by the clock generation block. For higher frequency data rates 2 × and 4× base data rates are not available.

Input clock frequency

Variable

Specifies the frequency of the PLL input reference clock. The Input clock frequency drop down menu is populated with all valid frequencies derived as a function of the data rate and base data rate. However, if you select fb_compensation as the bonding mode, then the input reference clock frequency is limited to the (data rate) / (PCS-PMA interface width).

The following table lists Standard and 10G datapath widths for the FPGA fabric-transceiver interface, the PCS-PMA interface, and the resulting frequencies for the tx_clkout and rx_clkout parallel clocks. In almost all cases, the parallel clock frequency is described by the following equation:

frequencyparallel clock = data rate/FPGA fabrictransceiver interface width

Note: The FPGA fabric transceiver interface width is always 128 bits for the GT datapath.
Table 151.  Datapath Width Support  

FPGA Fabric - Transceiver Interface Width

PCS-PMA Interface Width

tx_clkout and rx_clkout frequency

Standard Datapath

10G Datapath

8

8

data rate/8

10

10

data rate/10

16

8 or 16

data rate/16

20

10 or 20

data rate/20

32

16

32

data rate/32

40

20

40

data rate/40

50

40

data rate/50 7

64

32

data rate/32 8

64

64

data rate/64

66

40

data rate/66

7 For this datapath configuration, the tx_clkout frequency generated by the Low Latency PHY is the data rate /40. You must generate a /50 frequency clock from the /40 clock and feed this clock back into the tx_coreclkin. The rx_clkout frequency generated by the Low Latency PHY is /40 of the data rate. You must generate a /50 frequency from the recovered clock and feed this back into the rx_coreclkin.
8 For this datapath configuration, the tx_clkout frequency generated by the Low Latency PHY is the data rate/32. You must generate a /64 frequency clock from the /32 clock and feed this clock back into the tx_coreclkin. The rx_clkout frequency generated by the Low Latency PHY is the data rate/32. You must generate a /64 frequency from the recovered clock and feed this back into the rx_coreclkin

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