V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

8.3. Interlaken PHY General Parameters

This section describes the Interlaken PHY parameters you can set on the General tab.
Table 100.  Interlaken PHY General Options
Parameter Value Description
Device family

Arria V GZ

Stratix V

Specifies the device family.
Datapath mode




Specifies the mode of operation as Duplex, RX, or TX mode.
Lane rate

3125 Mbps

5000 Mbps

6250 Mbps

6375 Mbps

10312.5 Mbps

10312.5 Mbps

12500 Mbps


Specifies the lane data rate. The Input clock frequency and Base data rate parameters update automatically based on the Lane rate you specify.

Custom, user-defined, lane data rates are now supported. However, the you must choose a lane data rate that results in a standard board oscillator reference clock frequency to drive the pll_ref_clk and meet jitter requirements. Choosing a lane data rate that deviates from standard reference clock frequencies may result in custom board oscillator clock frequencies which may be prohibitively expensive or unavailable.

Number of lanes 1-24 Specifies the number of lanes in a link over which data is striped.
Metaframe length in words 5-8191

Specifies the number of words in a metaframe. The default value is 2048.

Although 5 -8191 words are valid metaframe length values, the current Interlaken PHY IP Core implementation requires a minimum of 128 Metaframe length for good, stable performance.

In simulation, Altera recommends that you use a smaller metaframe length to reduce simulation times.

Input clock frequency

Lane rate/<n>

Lane rate/80

Lane rate/64

Lane rate/50

Lane rate/40

Lane rate/32

Lane rate/25

Lane rate/20

Lane rate/16

Lane rate/12.5

Lane rate/10

Lane rate/8

Specifies the frequency of the input reference clock. The default value for the Input clock frequency is the Lane rate /20. Many reference clock frequencies are available.
PLL type



Specifies the PLL type.

The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of lane data rates and reference clock frequencies. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does. Because the CMU PLL is more versatile, it is specified as the default setting.

Base data rate

1 × Lane rate

2 × Lane rate

3 × Lane rate

This option allows you to specify a Base data rate to minimize the number of PLLs required to generate the clocks necessary for data transmission at different frequencies. Depending on the Lane rate you specify, the default Base data rate can be either 1, 2, or 4 times the Lane rate; however, you can change this value. The default value specified is for backwards compatibility with earlier Intel® Quartus® Prime software releases.