V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

10.3.1. General Options Parameters

The General Options tab allows you to set the basic parameters of your transceiver PHY.
Table 124.  Table 9-3.  Custom PHY General Options
Name Value Description
Device family

Arria V

Cyclone V

Stratix V

Specifies the device family. Arria V, Cyclone V, and Stratix V are available.
Parameter validation rules Custom GIGE Allows you to specify the transceiver protocol. Select Custom if you are not implementing 1.25 or 2.50GIGE.
Mode of operation Duplex TX RX You can select to transmit data, receive data, or both.
Number of lanes 1-32 The total number of lanes in each direction.
Enable lane bonding On/Off When enabled, a single clock drives multiple lanes, reducing clock skew. In Stratix V devices, up to 6 lanes can be bonded if you use an ATX PLL; 4 lanes can be bonded if you select the CMU PLL.
Bonding mode

Non-bonded or x1

Bonded or xN


Select Non-bonded or x1 to use separate clock sources for each channel. (This option is available for Cyclone V and Arria V devices.) If one PLL drives multiple channels, PLL merging is required. During compilation, the Intel® Quartus® Prime Fitter, merges all the PLLs that meet PLL merging requirements. Refer to Merging TX PLLs In Multiple Transceiver PHY Instances to observe PLL merging rules.

Select Bonded or xN to use the same clock source for up to 6 channels in a single transceiver bank, resulting in reduced clock skew. You must use contiguous channels when you select ×N bonding. In addition, you must place logical channel 0 in either physical channel 1 or 4. Physical channels 1 and 4 are indirect drivers of the ×N clock network.

Select fb_compensation (feedback compensation) to use the same clock source for multiple channels across different transceiver banks to reduce clock skew. (This option is only available for Stratix V devices.)

For more information about bonding, refer to "Transmitter Clock Network" in Transceiver Clocking in Arria V Devices in volume 2 of the Arria V Device Handbook.

For more information about bonding, refer to "Transmitter Clock Network" in Transceiver Clocking in Cyclone V Devices in volume 2 of the Cyclone V Device Handbook.

For more information about bonding, refer to "Bonded Channel Configurations Using the PLL Feedback Compensation Path" in Transceiver Clocking in Stratix V Devices in volume 2 of the Stratix V Device Handbook.

FPGA fabric transceiver interface width 8,10,16,20, 32,40 Specifies the total serialization factor, from an input or output pin to the MAC-layer logic.
PCS‑PMA interface width 8, 10, 16, 20 The PCS-PMA interface width depends on the FPGA fabric transceiver interface width and whether 8B/10B is enabled. The following combinations are available:
FPGA/XCVR 8B/10B PMA Interface Width
8 No 8
8 Yes 10
10 No 10
16 No 8 or 16
16 Yes 10 or 20
20 No 10 or 20
32 No 16
32 Yes 20
40 No 20
PLL type



The CMU PLL is available for Arria V and Cyclone V devices.

For Stratix V devices, you can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of data rates and reference clock frequencies. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does.

Because the CMU PLL is more versatile, it is specified as the default setting. An informational message displays in the message pane telling you whether the chosen settings for Data rate and Input clock frequency are legal for the CMU PLL, or for both the CMU and ATX PLLs.

Data rate 622-11000 Mbps Specifies the data rate. The possible data rates depend upon the device and configuration specified.
Base data rate

1 × Data rate

2 × Data rate

4 × Data rate

The base data rate is the frequency of the clock input to the PLL. Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission. By selecting an appropriate base data rate, you can change data rates by changing the divider used by the clock generation block. For higher frequency data rates 2 × and 4× base data rates are not available.
Input clock frequency Variable Specifies the frequency of the PLL input reference clock.
Additional Options
Enable TX Bitslip On/Off When enabled, the TX bitslip word aligner is operational.
Create rx_coreclkin port On/Off This is an optional clock to drive the coreclk of the RX PCS
Create tx_coreclkin port On/Off This is an optional clock to drive the coreclk of the TX PCS
Create rx_recovered_clk port On/Off When enabled, the RX recovered clock is an output.
Create optional ports On/Off When you turn this option on, the following signals are added to the top level of your transceiver for each lane:
  • tx_forceelecidle
  • rx_is_lockedtoref
  • rx_is_lockedtodata
  • rx_signaldetect
Enable Avalon data interfaces and bit reversal On/Off When you turn this option On, the order of symbols is changed. This option is typically required if you are planning to import your Custom PHY IP Core into a Qsys system.
Enable embedded reset control On/Off When On, the automatic reset controller initiates the reset sequence for the transceiver. When Off you can design your own reset logic using tx_analogreset , rx_analogreset, tx_digitalreset, rx_digitalreset, and pll_powerdown which are top‑level ports of the Custom Transceiver PHY. You may also use the Transceiver PHY Reset Controller' to reset the transceivers. For more information, refer to the Transceiver Reconfiguration Controller IP Core . By default, the CDR circuitry is in automatic lock mode whether you use the embedded reset controller or design your own reset logic. You can switch the CDR to manual mode by writing the pma_rx_setlocktodata or pma_rx_set_locktoref registers to 1. If either the pma_rx_set_locktodata and pma_rx_set_locktoref is set, the CDR automatic lock mode is disabled.
Table 125.  Reset Mode The CDR can be put in either manual or automatic mode. The CDR mode is controlled with the pma_rx_set_locktodata and pma_rx_set_locktoref registers. This table shows the required settings to control the CDR mode.
rx_set_locktoref rx_set_locktodata CDR Lock Mode
1 0 Manual RX CDR locked to reference
X 1 Manual RX CDR locked to data
0 0 Automatic RX CDR