V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

16.7. Interfaces

The Native PHY includes several interfaces that are common to all parameterizations.

The Native PHY allows you to enable ports, even for disabled blocks to facilitate dynamic reconfiguration.

The Native PHY uses the following prefixes for port names:

  • Standard PCS ports—tx_std, rx_std

The port descriptions use the following variables to represent parameters:

  • <n>—The number of lanes
  • <p>—The number of PLLs
  • <r>—The number of CDR references clocks selected

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