V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

20.5.2.17. XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE

Pin Planner and Assignment Editor Name

Receiver Linear Equalizer Control (PCI Express)

Description

If enabled equalizer gain control is driven by the PCS block for PCI Express. If disabled equalizer gain control is determined by the  XCVR_RX_LINEAR_EQUALIZER_SETTING

Options

TRUE

FALSE

Assign To

Pin - RX serial data

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