V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

6.1.1. Features

Table 69.  PHY Features
Feature Description
Multiple operating speeds 1G, 2.5G, 5G, and 10G.
MAC-side interface 16-bit GMII for 1G and 2.5G.
32-bit XGMII for 1G/2.5G/5G/10G (USXGMII).
64-bit XGMII for 10G.
Network-side interface 1.25 Gbps for 1G.
3.125 Gbps for 2.5G.
10.3125 Gbps for 1G/2.5G/5G/10G (USXGMII).
Avalon® Memory-Mapped interface Provides access to the configuration registers of the PHY.
PCS function 1000BASE-X for 1G and 2.5G.
10GBASE-R for 10G.
USXGMII PCS for 1G/2.5G/5G/10G
Auto-negotiation

Implements clause 37. Supported in 1GbE only.

USXGMII Auto-negotiation supported in the 1G/2.5G/5G/10G (USXGMII) configuration.

IEEE 1588v2 Provides the required latency to the MAC if the MAC enables the IEEE 1588v2 feature.
Sync-E Provides the clock for Sync-E implementation.

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