V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

10.4.4. Optional Reset Control and Status Interface

This topic describes the signals in the optional reset control and status interface. These signals are available if you do not enable the embedded reset controller.
Table 140.  Avalon-ST RX Interface
Signal Name Direction Description
pll_powerdown Input When asserted, resets the TX PLL.
tx_digitalreset[<n>-1:0] Input When asserted, reset all blocks in the TX PCS. If your design includes bonded TX PCS channels, refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design.
tx_analogreset[<n>-1:0] Input When asserted, resets all blocks in the TX PMA.
Note: For Arria V devices, while compiling a multi-channel transceiver design, you will see a compile warning (12020) in Intel® Quartus® Prime software related to the signal width of tx_analogreset. You can safely ignore this warning. Also, per-channel TX analog reset is not supported in Intel® Quartus® Prime software. Channel 0 TX analog resets all the transceiver channels.
tx_cal_busy[<n>-1:0] Output When asserted, indicates that the initial TX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. You must hold the channel in reset until calibration completes.
rx_digitalreset[<n>-1:0] Input When asserted, resets the RX PCS.
rx_analogreset[<n>-1:0] Input When asserted, resets the RX CDR.
rx_cal_busy[<n>-1:0] Output When asserted, indicates that the initial RX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.