V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

16.5.2. TX PLL Parameters

This section allows you to define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a separate tab for each TX PLL.
Table 299.  TX PLL Parameters




PLL type


This is the only PLL type available.

PLL base data rate

Device Dependent

Shows the base data rate of the clock input to the TX PLL.The PLL base data rate is computed from the TX local clock division factor multiplied by the Data rate.

Select a PLL base data rate that minimizes the number of PLLs required to generate all the clocks for data transmission. By selecting an appropriate PLL base data rate, you can change data rates by changing the TX local clock division factor used by the clock generation block.

Reference clock frequency

Device Dependent

Specifies the frequency of the reference clock for the Selected reference clock source index you specify. You can define a single frequency for each PLL. You can use the Transceiver Reconfiguration Controller to dynamically change the reference clock input to the PLL.

Note that the list of frequencies updates dynamically when you change the Data rate. The Input clock frequency drop down menu is populated with all valid frequencies derived as a function of the Data rate and Base data rate.

Selected reference clock source


You can define up to 5 reference clock sources for the PLLs in your core. The Reference clock frequency selected for index 0, is assigned to TX PLL<0>. The Reference clock frequency selected for index 1, is assigned to TX PLL<1>, and so on.

Selected clock network

x1 ×N

Selects the clock network for the TX PLL.

In non-bonded mode, each channel is assigned to one PLL. PLL merging is required when multiple channels are assigned to one PLL. During compilation, the Intel® Quartus® Prime Fitter, merges all the PLLs that meet PLL merging requirements. Refer to Merging TX PLLs In Multiple Transceiver PHY Instances for more details.