V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

7.16. XAUI PHY Register Interface and Register Descriptions

This section describes the register interface and descriptions for the IP core.

The Avalon-MM PHY management interface provides access to the XAUI PHY IP Core PCS, PMA, and transceiver reconfiguration registers.

Table 95.  Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk Input

Avalon-MM clock input.

There is no frequency restriction for Stratix V devices; however, if you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency range of phy_mgmt_clk to 100–150 MHz to meet the specification for the transceiver reconfiguration clock. For Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix IV GX the frequency range is 37.5–50 MHz.

phy_mgmt_clk_reset Input Global reset signal that resets the entire XAUI PHY. This signal is active high and level sensitive.
phy_mgmt_addr[8:0] Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0] Input 32-bit input data.
phy_mgmt_readdata[31:0] Output 32-bit output data.
phy_mgmt_write Input Write signal. Asserted high.
phy_mgmt_read Input Read signal. Asserted high.
phy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.

For more information about the Avalon-MM interface, including timing diagrams, refer to the Avalon Interface Specifications.

The following table specifies the registers that you can access using the Avalon-MM PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.

Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 96.  XAUI PHY IP Core Registers
Word Addr Bits R/W Register Name Description
PMA Common Control and Status Registers
0x021 [31:0] RW cal_blk_powerdown Writing a 1 to channel < n > powers down the calibration block for channel < n >. This register is not available for Stratix V devices.
0x022 [31:0] R pma_tx_pll_is_locked Bit[P] indicates that the TX CMU PLL (P) is locked to the input reference clock. There is typically one pma_tx_pll_is_locked bit per system. This register is not available for Arria V, Arria V GZ, Cyclone V, or Stratix V devices.
Reset Control Registers–Automatic Reset Controller
0x041 [31:0] RW reset_ch_bitmask

Bit mask for reset registers at addresses 0x042 and 0x044. The default value is all 1s. Channel < n > can be reset when

bit< n > = 1.

0x042 [1:0] W reset_control(write) Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask. This bit self-clears.
R reset_status(read) Reading bit 0 returns the status of the reset controller TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit. This bit self-clears.
Reset Controls –Manual Mode
0x044 [31:4,0] RW Reserved It is safe to write 0s to reserved bits.
[1] RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted, resetting all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.
[2] RW reset_rx_analog Writing a 1 causes the internal RX analog reset signal to be asserted, resetting the RX analog logic of all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.
[3] RW reset_rx_digital Writing a 1 causes the RX digital reset signal to be asserted, resetting the RX digital channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.
PMA Control and Status Registers
0x061 [31:0] RW phy_serial_loopback Writing a 1 to channel < n > puts channel < n > in serial loopback mode. For information about pre- or post-CDR serial loopback modes, refer to Loopback Modes.
0x064 [31:0] RW pma_rx_set_locktodata When set, programs the RX CDR PLL to lock to the incoming data. Bit < n > corresponds to channel < n >.
0x065 [31:0] RW pma_rx_set_locktoref When set, programs the RX CDR PLL to lock to the reference clock. Bit < n > corresponds to channel < n >.
0x066 [31:0] RO pma_rx_is_lockedtodata When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit < n > corresponds to channel < n >.
0x067 [31:0] RO pma_rx_is_lockedtoref When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit < n > corresponds to channel < n >.
XAUI PCS
0x082 [31:4] - Reserved -
[3:0] RW invpolarity[3:0]

Inverts the polarity of corresponding bit on the RX interface. Bit 0 maps to lane 0 and so on. This register is only available in the hard XAUI implementation.

To block: Word aligner.

0x083 [31:4] - Reserved -
[3:0] RW invpolarity[3:0]

Inverts the polarity of corresponding bit on the TX interface. Bit 0 maps to lane 0 and so on. This register is only available in the hard XAUI implementation.

To block: Serializer.

0x084 [31:16] - Reserved -
[15:8] R patterndetect[7:0]

When asserted, indicates that the programmed word alignment pattern has been detected in the current word boundary. The RX pattern detect signal is 2 bits wide per channel or 8 bits per XAUI link. Reading the value of the patterndetect registers clears the bits.This register is only available in the hard XAUI implementation.

From block: Word aligner.

[7:0] syncstatus[7:0]

Records the synchronization status of the corresponding bit. The RX sync status register has 2 bits per channel for a total of 8 bits per hard XAUI link. The RX sync status register has 1 bit per channel for a total of 4 bits per soft XAUI link; soft XAUI uses bits 0–3. Reading the value of the syncstatus register clears the bits.

From block: Word aligner.

0x085 [31:16] - Reserved -
[15:8] R errdetect[7:0]

When set, indicates that a received 10-bit code group has an 8B/10B code violation or disparity error. It is used along with disperr to differentiate between a code violation error, a disparity error, or both. There are 2 bits per RX channel for a total of 8 bits per XAUI link. Reading the value of the errdetect register clears the bits.

From block: 8B/10B decoder.

[7:0] disperr[7:0]

Indicates that the received 10-bit code or data group has a disparity error. When set, the corresponding errdetect bits are also set. There are 2 bits per RX channel for a total of 8 bits per XAUI link. Reading the value of the errdetect register clears the bits

From block: 8B/10B decoder.

0x086 [31:8] - Reserved -
[7:4] R, sticky phase_comp_fifo_error[3:0]

Indicates a RX phase compensation FIFO overflow or underrun condition on the corresponding lane. Reading the value of the phase_comp_fifo_error register clears the bits. This register is only available in the hard XAUI implementation

From block: RX phase compensation FIFO.

[3:0] rlv[3:0]

Indicates a run length violation. Asserted if the number of consecutive 1s or 0s exceeds the number that was set in the Runlength check option. Bits 0-3 correspond to lanes 0-3, respectively. Reading the value of the RLV register clears the bits. This register is only available in the hard XAUI implementation.

From block: Word aligner.

0x087 [31:16] - Reserved -
[15:8] R, sticky rmfifodatainserted[7:0]

When asserted, indicates that the RX rate match block inserted a ||R|| column. Goes high for one clock cycle per inserted ||R|| column. Reading the value of the rmfifodatainserted register clears the bits. This register is only available in the hard XAUI implementation.

From block: Rate match FIFO.

[7:0] rmfifodatadeleted[7:0]

When asserted, indicates that the rate match block has deleted an ||R|| column. The flag goes high for one clock cycle per deleted ||R|| column. There are 2 bits for each lane. Reading the value of the rmfifodatadeleted register clears the bits. This register is only available in the hard XAUI implementation.

From block: Rate match FIFO.

0x088 [31:8] - Reserved -
[7:4] R, sticky rmfifofull[3:0]

When asserted, indicates that rate match FIFO is full (20 words). Bits 0-3 correspond to lanes 0-3, respectively. Reading the value of the rmfifofull register clears the bits. This register is only available in the hard XAUI implementation

From block: Rate match FIFO.

[3:0] rmfifoempty[3:0]

When asserted, indicates that the rate match FIFO is empty (5 words). Bits 0-3 correspond to lanes 0-3, respectively. Reading the value of the rmfifoempty register clears the bits. This register is only available in the hard XAUI implementation

From block: Rate match FIFO.

0x089 [31:3] - Reserved -
[2:0] R, sticky phase_comp_fifo_error[2:0]

Indicates a TX phase compensation FIFO overflow or underrun condition on the corresponding lane. Reading the value of the phase_comp_fifo_error register clears the bits. This register is only available in the hard XAUI implementation

From block: TX phase compensation FIFO.

0x08a [0] RW simulation_flag Setting this bit to 1 shortens the duration of reset and loss timer when simulating. Altera recommends that you keep this bit set during simulation.

For more information about the individual PCS blocks, refer to the Transceiver Architecture chapters of the appropriate device handbook.

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