V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

8.6. Interlaken PHY Interfaces

This section describes the Interlaken PHY interfaces.

The following figure illustrates the top-level signals of the Interlaken PHY IP Core; <n> is the channel number so that the width of tx_data in 4-lane instantiation is [263:0].

Figure 46. Top-Level Interlaken PHY Signals
Note: The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used to define interfaces in the _hw.tcl. writing.

For more information about _hw.tcl, files refer to the Component Interface Tcl Reference chapter in volume 1 of the Intel® Quartus® Prime Handbook.