Visible to Intel only — GUID: nik1398984361695
Ixiasoft
Visible to Intel only — GUID: nik1398984361695
Ixiasoft
20.3.2.13. XCVR_RX_SD_THRESHOLD
Pin Planner and Assignment Editor Name
Receiver Signal Detection Voltage Threshold
Description
Specifies signal detection voltage threshold level, Vth. The following encodings are defined:
- SDLV_50MV=7
- SDLV_45MV=6
- SDLV_40MV=5
- SDLV_35MV=4
- SDLV_30MV=3
- SDLV_25MV=2
- SDLV_20MV=1
- SDLV_15MV=0
For the PCIe PIPE PHY, SATA, and SAS.
The signal detect output is high when the receiver peak-to-peak differential voltage (diff p-p) > Vth x 4. For example, a setting of 6 translates to peak-to-peak differential voltage of 180mV (4*45mV). The Vdiff p-p must be > 180mV to turn on the signal detect circuit.
Options
- 0-7
Assign To
Pin - RX serial data
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