V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

4.11.5. Dynamic Reconfiguration Interface Signals

You can use the dynamic reconfiguration interface signals to dynamically change between 1G,10G data rates and AN or LT mode. These signals also used to update TX coefficients during Link Training..
Table 39.  Dynamic Reconfiguration Interface Signals
Signal Name Direction Description
reconfig_to_xcvr

[(<n>70-1):0]

Input Reconfiguration signals from the Reconfiguration Design Example. <n> grows linearly with the number of reconfiguration interfaces.
reconfig_from_xcvr

[(<n>46-1):0]

Output Reconfiguration signals to the Reconfiguration Design Example. <n> grows linearly with the number of reconfiguration interfaces.
rc_busy Input When asserted, indicates that reconfiguration is in progress.
lt_start_rc Output When asserted, starts the TX PMA equalization reconfiguration.
main_rc[5:0] Output The main TX equalization tap value which is the same as VOD. The following example mappings to the VOD settings are defined:
  • 6'b111111: FIR_MAIN_12P6MA
  • 6'b111110: FIR_MAIN_12P4MA
  • 6'b000001: FIR_MAIN_P2MA
  • 6'b000000: FIR_MAIN_DISABLED
post_rc[4:0] Output The post‑cursor TX equalization tap value. This signal translates to the first post-tap settings. The following example mappings are defined:
  • 5'b11111: FIR_1PT_6P2MA
  • 5'b11110: FIR_1PT_6P0MA
  • 5'b00001: FIR_1PT_P2MA
  • 5'b00000: FIR_1PT_DISABLED
pre_rc[3:0] Output The pre‑cursor TX equalization tap value. This signal translates to pre-tap settings. The following example mappings are defined:
  • 4'b1111: FIR_PRE_3P0MA
  • 4'b1110: FIR_PRE_P28MA
  • 4'b0001: FIR_PRE_P2MA
  • 4'b0000: FIR_PRE_DISABLED
tap_to_upd[2:0] Output Specifies the TX equalization tap to update to optimize signal quality. The following encodings are defined:
  • 3'b100: main tap
  • 3'b010: post‑tap
  • 3'b001: pre‑tap
seq_start_rc Output When asserted, starts PCS reconfiguration.
pcs_mode_rc[5:0] Output Specifies the PCS mode for reconfig using 1‑hot encoding. The following modes are defined:
  • 6'b000001: Auto‑Negotiation mode
  • 6'b000010: Link Training mode
  • 6'b000100: 10GBASE‑KR data mode
  • 6'b001000: GigE data mode
  • 6'b010000: Reserved
  • 6'b100000:10G data mode with FEC
dfe_start_rc Output

When asserted, starts the RX DFE equalization of the PMA.

dfe_mode[1:0] Output Specifies the DFE operation mode. Valid at the rising edge of the def_start_rc signal and held until the falling edge of the rc_busy signal. The following encodings are defined:
  • 2'b00: Disable DFE
  • 2'b01: DFE triggered mode
  • 2'b10: Reserved
  • def_start_rcd'b11: Reserved
ctle_start_rc Output When asserted, starts continuous time-linear equalization (CTLE) reconfiguration.
ctle_mode[1:0] Output Specifies CTLE mode. These signals are valid at the rising edge of the ctle_start_rc signal and held until the falling edge of the rc_busy signal. The following encodings are defined:
  • 2'b00: ctle_rc[3:0] drives the value of CTLE set during link training
  • 2'b01: Reserved
  • 2b'10: Reserved
  • 2'b11: Reserved
ctle_rc[3:0] Output RX CTLE value. This signal is valid at the rising edge of the ctle_start_rc signal and held until the falling edge of the rc_busy signal. The valid range of values is 4'b0000-4'b1111.
mode_1g_10gbar Input This signal indicates the requested mode for the channel. A 1 indicates 1G mode and a 0 indicates 10G mode. This signal is only used when the sequencer which performs automatic speed detection is disabled.
en_lcl_rxeq Output This signal is not used. You can leave this unconnected.
rxeq_done Input Link training requires RX equalization to be complete. Tie this signal to 1 to indicate that RX equalization is complete.

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