14. Arria V Transceiver Native PHY IP Core
The Arria V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports. The Arria V Transceiver Native PHY IP Core provides the following datapaths:
- Standard PCS—When you enable the Standard PCS, you can select the PCS functions and control and status ports that your transceiver PHY requires.
- PMA Direct—When you select PMA Direct mode, the Native PHY provides direct access to the PMA from the FPGA fabric; consequently, the latency for transmitted and received data is lower. However, you must implement any PCS function that your design requires in the FPGA fabric. PMA Direct mode is supported for Arria V GT, ST, and GZ devices only.
The Native Transceiver PHY does not include an embedded reset controller. You can either design custom reset logic or incorporate Altera’s “Transceiver PHY Reset Controller IP Core” to implement reset functionality. The Native Transceiver PHY’s primary use in Arria V GT devices is for data rates greater than 6.5536 Gbps.
As the following figure illustrates, TX PLL and clock data recovery (CDR) reference clocks from the pins of the device are input to the PLL module and CDR logic. When enabled, the Standard PCS drives TX parallel data and receives RX parallel data. In PMA Direct mode, the PMA serializes TX data it receives from the fabric and drives RX data to the fabric.
In a typical design, the separately instantiated Transceiver PHY Reset Controller drives reset signals to Native PHY and receives calibration and locked status signal from the Native PHY. The Native PHY reconfiguration buses connect the external Transceiver Reconfiguration Controller for calibration and dynamic reconfiguration of the channel and PLLs.
You specify the initial configuration when you parameterize the IP core. The Transceiver Native PHY IP Core connects to the “Transceiver Reconfiguration Controller IP Core” to dynamically change reference clocks, PLL connectivity, and the channel configurations at runtime.
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