V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
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Document Table of Contents

13.4.2. PMA Parameters for Stratix V Native PHY

This section describes the PMA parameters for the Stratix V native PHY.

Table 182.  PMA Options

The following table describes the options available for the PMA. For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Stratix V Devices.

Some parameters have ranges where the value is specified as Device Dependent. For such parameters, the possible range of frequencies and bandwidths depends on the device, speed grade, and other design characteristics. Refer to the Stratix V Device Datasheet for specific data for Stratix V devices.

Parameter Range Description
Data rate Device Dependent Specifies the data rate.
TX local clock division factor 1, 2, 4, 8 Specifies the value of the divider available in the transceiver channels to divide the input clock to generate the correct frequencies for the parallel and serial clocks.
TX PLL base data rate Device Dependent Specifies the base data rate for the clock input to the TX PLL. Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission. By selecting an appropriate base data rate, you can change data rates by changing the divider used by the clock generation block.
PLL base data rate Device Dependent Shows the base data rate of the clock input to the TX PLL. The PLL base data rate is computed from the TX local clock division factor multiplied by the data rate.

Select a PLL base data rate that minimizes the number of PLLs required to generate all the clocks for data transmission. By selecting an appropriate PLL base data rate, you can change data rates by changing the TX local clock division factor used by the clock generation block.

TX PMA Parameters

Table 183.  TX PMA Parameters

The following table describes the TX PMA options you can specify.

For more information about the TX CMU, ATX, and fractional PLLs, refer to the Stratix V PLLs section in Transceiver Architecture in Stratix V Devices.

Parameter Range Description
Enable TX PLL dynamic reconfiguration On/Off When you turn this option On, you can dynamically reconfigure the PLL to use a different reference clock input. This option is also required to simulate TX PLL reconfiguration. If you turn this option On, the Intel® Quartus® Prime Fitter prevents PLL merging by default; however, you can specify merging using the XCVR_TX_PLL_RECONFIG_GROUP QSF assignment.
Use external TX PLL On/Off

When you turn this option On, the Native PHY does not automatically instantiate a TX PLL. Instead, you must instantiate an external PLL and connect it to the ext_pll_clk[<p> -1 : 0] port of the Stratix Native PHY.

Use the Stratix V Transceiver PLL IP Core to instantiate a CMU or ATX PLL. Use Altera Phase-Locked Loop (ALTERA_ PLL) Megafunction to instantiate a fractional PLL.

Number of TX PLLs 1-4

Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates. If your design does not require transceiver TX PLL dynamic reconfiguration, set this value to 1. The number of actual physical PLLs that are implemented depends on the selected clock network. Each channel can dynamically select between n PLLs, where n is the number of PLLs specified for this parameter.

Note: Refer to Transceiver Clocking in Stratix V Devices chapter for more details.
Main TX PLL logical index 0-3 Specifies the index of the TX PLL used in the initial configuration.
Number of TX PLL reference clocks 1-5 Specifies the total number of reference clocks that are shared by all of the PLLs.
Table 184.  TX PLL ParametersThe following table describes how you can define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a separate tab for each TX PLL.
Parameter Range Description
PLL type

CMU

ATX

You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of data rates and reference clock frequencies. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does.

Because the CMU PLL is more versatile, it is specified as the default setting. An error message displays in the message pane if the settings chosen for Data rate and Input clock frequency are not supported for selected PLL.

PLL base data rate Device Dependent Shows the base data rate of the clock input to the TX PLL.The PLL base data rate is computed from the TX local clock division factor multiplied by the Data rate. Select a PLL base data rate that minimizes the number of PLLs required to generate all the clocks for data transmission. By selecting an appropriate PLL base data rate, you can change data rates by changing the TX local clock division factor used by the clock generation block.
Reference clock frequency Device Dependent Specifies the frequency of the reference clock for the Selected reference clock source index you specify. You can define a single frequency for each PLL. You can use the Transceiver Reconfiguration Controller shown in Stratix V Native Transceiver PHY IP Core to dynamically change the reference clock input to the PLL.

Note that the list of frequencies updates dynamically when you change the Data rate.

The Input clock frequency drop down menu is populated with all valid frequencies derived as a function of the data rate and base data rate. However, if fb_compensation is selected as the bonding mode then the input reference clock frequency is limited to the data rate divided by the PCS-PMA interface width.
Selected reference clock source 0-4 You can define up to 5 frequencies for the PLLs in your core. The Reference clock frequency selected for index 0 , is assigned to TX PLL<0>. The Reference clock frequency selected for index 1 , is assigned to TX PLL<1>, and so on.

RX CDR Options

Table 185.   RX PMA ParametersThe following table describes the RX CDR options you can specify. For more information about the CDR circuitry, refer to the Receiver Clock Data Recovery Unit section in Clock Networks and PLLs in Stratix V Devices.
Parameter Range Description
Enable CDR dynamic reconfiguration On/Off When you turn this option On, you can dynamically change the reference clock input the CDR circuit. This option is also required to simulate TX PLL reconfiguration.
Number of CDR reference clocks 1-5 Specifies the number of reference clocks for the CDRs.
Selected CDR reference clock 0-4 Specifies the index of the selected CDR reference clock.
Selected CDR reference clock frequency Device Dependent Specifies the frequency of the clock input to the CDR.
PPM detector threshold +/- 1000 PPM Specifies the maximum PPM difference the CDR can tolerate between the input reference clock and the recovered clock.
Enable rx_is_lockedtodata port On/Off When you turn this option On, the rx_is_lockedtodata port is an output of the PMA.
Enable rx_is_lockedtoref port On/Off When you turn this option On, the rx_is_lockedtoref port is an output of the PMA.
Enable rx_set_locktodata and rx_set_locktoref ports On/Off When you turn this option On, the rx_set_locktodata and rx_set_locktoref ports are outputs of the PMA.
Enable rx_pma_bitslip_port On/Off When you turn this option On, the rx_pma_bitslip is an input to the core. The deserializer slips one clock edge each time this signal is asserted. You can use this feature to minimize uncertainty in the serialization process as required by protocols that require a datapath with deterministic latency such as CPRI.
Enable rx_seriallpbken port On/Off When you turn this option On, the rx_seriallpbken is an input to the core. When your drive a 1 on this input port, the PMA operates in loopback mode with TX data looped back to the RX channel.

PMA Optional Ports

Table 186.  RX PMA Parameters

The following table describes the optional ports you can include in your IP Core. The QPI interface implements the Intel Quickpath Interconnect.

For more information about the CDR circuitry, refer to the Receiver Clock Data Recovery Unit section in Clock Networks and PLLs in Stratix V Devices.

Parameter Range Description
Enable tx_pma_qpipullup port (QPI) On/Off When you turn this option On, the core includes tx_pma_qpipullup control input port. This port is only used for QPI applications.
Enable tx_pma_qpipulldn port (QPI) On/Off When you turn this option On, the core includes tx_pma_qpipulldn control input port. This port is only used for QPI applications.
Enable tx_pma_txdetectrx port (QPI) On/Off When you turn this option On, the core includes tx_pma_txdetectrx control input port. This port is only used for QPI applications. The RX detect block in the TX PMA detects the presence of a receiver at the other end of the channel. After receiving a tx_pma_txdetectrx request, the receiver detect block initiates the detection process.
Enable tx_pma_rxfound port (QPI) On /Off When you turn this option On, the core includes tx_pma_rxfound output status port. This port is only used for QPI applications. The RX detect block in the TX PMA detects the presence of a receiver at the other end of the channel. tx_pma_rxfound indicates the result of detection.
Enable rx_pma_qpipulldn port (QPI) On/Off When you turn this option On, the core includes the rx_pma_qpipulldn port. This port is only used for QPI applications.
Enable rx_pma_clkout port On/Off When you turn this option On, the RX parallel clock which is recovered from the serial received data is an output of the PMA.
Enable rx_is_lockedtodata port On/Off When you turn this option On, the rx_is_lockedtodata port is an output of the PMA.
Enable rx_is_lockedtoref port On/Off When you turn this option On, the rx_is_lockedtoref port is an output of the PMA.
Enable rx_set_lockedtodata and rx_set_locktoref ports On/Off When you turn this option On, the rx_set_lockedtdata and rx_set_lockedtoref ports are outputs of the PMA.
Enable rx_clkslip port On/Off When you turn this option On, the rx_clkslip control input port is enabled. The deserializer slips one clock edge each time this signal is asserted. You can use this feature to minimize uncertainty in the serialization process as required by protocols that require a datapath with deterministic latency such as CPRI.
Enable rx_seriallpbken port On/Off When you turn this option On, the rx_seriallpbken is an input to the core. When your drive a 1 on this input port, the PMA operates in loopback mode with TX data looped back to the RX channel.

The following table lists the best case latency for the most significant bit of a word for the RX deserializer for the PMA Direct datapath. For example, for an 8-bit interface width, the latencies in UI are 11 for bit 7, 12 for bit 6, 13 for bit 5, and so on.

Table 187.  Latency for RX Deserialization in Stratix V Devices
FPGA Fabric Interface Width Stratix V Latency in UI
8 bits 11
10 bits 13
16 bits 19
20 bits 23
32 bits 35
40 bits 43
64 bits 99
80 bits 123
Table 188.  Latency for TX Serialization in Stratix V DevicesThe following table lists the best- case latency for the LSB of the TX serializer for all supported interface widths for the PMA Direct datapath.
FPGA Fabric Interface Width Stratix V Latency in UI
8 bits 44
10 bits 54
16 bits 68
20 bits 84
32 bits 100
40 bits 124
64 bits 132
80 bits 164

The following tables lists the bits used for all FPGA fabric to PMA interface widths. Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the TX and RX parallel data ports. However, depending upon the interface width selected not all bits on the bus will be active. The following table lists which bits are active for each FPGA Fabric Interface Width selection. For example, if your interface is 16 bits, the active bits on the bus are [17:10] and [7:0] of the 80 bit bus. The non-active bits are tied to ground.

Table 189.  Active Bits for Each Fabric Interface Width in PMA Direct Mode
FPGA Fabric Interface Width Bus Bits Used
8 bits [7:0]
10 bits [9:0]
16 bits {[17:10], [7:0]}
20 bits [19:0]
32 bits {[37:30], [27:20], [17:10], [7:0]}
40 bits [39:0]
64 bits {[77:70], [67:60], [57:50], [47:40], [37:30], [27:20], [17:10], [7:0]}
80 bits [79:0]

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