V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

17.12. Transceiver Reconfiguration Controller AEQ Registers

Adaptive equalization compensates for backplane losses and dispersion which degrade signal quality.

AEQ can be run once to help control the four-stage continuous time linear equalizer (CTLE), which is a manual tool that compensates for backplane losses and dispersion.

The following table lists the direct AEQ registers that you can access using Avalon-MM reads and writes on reconfiguration management interface.

Note: All undefined register bits are reserved.
Table 331.   AEQ Registers
Reconfig Addr Bits R/W Register Name Description
7’h28 [9:0] RW logical channel number The logical channel number of the AEQ hardware to be accessed. Must be specified when performing dynamic updates. The Transceiver Reconfiguration Controller maps the logical address to the physical address.
7’h2A [9] R control and status

Error.When asserted, indicates an error. This bit is asserted when the channel address is invalid.

[8] R Busy. When asserted, indicates that a reconfiguration operation is in progress.
[1] W Read. Writing a 1 to this bit triggers a read operation.
[0] W Write. Writing a 1 to this bit triggers a write operation.
7’h2B [3:0] RW aeq_offset Specifies the address of the AEQ register to be read or written. Refer to Table 332 for details.
7’h2C [15:0] RW data Specifies the read or write data.

The following table describes the AEQ registers that you can access to change AEQ settings.

Note: All undefined register bits are reserved.
Table 332.  AEQ Offsets and Values
Offset Bits R/W Register Name Description Default Value
0x0 [8] R adapt_done When asserted, indicates that adaptation has completed. In One-Time Adaptation Mode, AEQ stops searching new EQ settings even if the signal quality of incoming serial data is inadequate.

For some extreme cases, when the channel loss is too much for AEQ to compensate, the adapt_done signal may never be asserted. The AEQ engine can take up to 50,000 reconfiguration clock cycles before selecting the final equalization settings.

[1:0] RW mode

Specifies the following address modes:

  • 2’b00: Low power manual equalization mode
  • 2’b01: One-time AEQ adaptation at power up
  • 2’b11: Reserved
0x1 [3:0] R equalization results This is the value set by the automatic AEQ adaptation performed at startup. If you choose to perform manual equalization using the linear equalizer, you can use this value as a reference. Although automatic and manual equalization do not provide identical functionality, specifying this value enables manual equalization to approximate the original setting. 4’b0000

Refer to Changing Transceiver Settings Using Register-Based Reconfiguration for the procedures you can use to control AEQ.