V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

9.14. Enabling Dynamic PMA Tuning for PCIe Gen3

“Section 4.2.3 Link Equalization Procedure for 8.0 GT/s Data Rate” in the PCI Express Base Specification, Rev. 3.0 provides detailed information about the four-stage link equalization procedure. However, in some instances you may want to override the specified four-stage link equalization procedure to dynamically tune PMA settings. Follow these steps to override Gen3 equalization:
  1. Connect the Transceiver Reconfiguration Controller IP Core to your PHY IP Core for PCI Express as shown in PCI Express PIPE IP Core Top-Level Modules.
  2. For each transmitter port, use the Intel® Quartus® Prime Assignment Editor to assign the Transmitter VOD/Preemphasis Control Source the value RAM_CTL.
  3. Recompile your design.
You can now use the Transceiver Reconfiguration Controller to change VOD and pre-emphasis settings.

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