V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

13.4.3. Standard PCS Parameters for the Native PHY

This section shows the complete datapath and clocking for the Standard PCS and defines the parameters available in the GUI to enable or disable the individual blocks in the Standard PCS.

Figure 66. The Standard PCS Datapath
Table 190.  General and Datapath ParametersThe following table describes the general and datapath options for the Standard PCS.
Parameter Range Description
Standard PCS protocol mode

basic

cpri

gige

srio_2p1

Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the Standard PCS datapath. Use the following guidelines to select a protocol mode:
  • basic -select this mode for when none of the other options are appropriate. You should also select this mode to enable diagnostics, such as loopback.
  • cpri select this mode if you intend to implement CPRI or another protocol that requires deterministic latency. Intel recommends that you select the appropriate CPRI preset for the CPRI protocol.
  • gige -select this mode if you intend to implement Gigabit Ethernet. Intel recommends that you select the appropriate GIGE preset for the Ethernet bandwidth you intend to implement.
  • srio_2p1 -select this mode if you intend to implement the Serial RapidIO protocol.
Standard PCS/PMA interface width

8, 10, 16,

20, 32, 40

64, 80

Specifies the width of the datapath that connects the FPGA fabric to the PMA. The transceiver interface width depends upon whether you enable 8B/10B. To simplify connectivity between the FPGA fabric and PMA, the bus bits used are not contiguous for 16‑ and 32‑bit buses. 16‑, 32‑, and 64‑bit buses. Refer to Table 189 for the bits used.
FPGA fabric/Standard TX PCS interface width 8, 10, 16, 20 Shows the FPGA fabric to TX PCS interface width which is calculated from the Standard PCS/PMA interface width.
FPGA fabric/Standard RX PCS interface width 8, 10, 16, 20 Shows the FPGA fabric to RX PCS interface width which is calculated from the Standard PCS/PMA interface width.
Enable Standard PCS low latency mode On/ Off When you turn this option On, all PCS functions are disabled. This option creates a the lowest latency Native PHY that allows dynamic reconfigure between multiple PCS datapaths.

Phase Compensation FIFO

The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the low-speed parallel clock and FPGA fabric interface clock. The following table describes the options for the phase compensation FIFO.

Table 191.  Phase Compensation FIFO Parameters
Parameter Range Description
TX FIFO mode

low_latency

register_fifo

The following 2 modes are possible:
  • low_latency : This mode adds 3-4 cycles of latency to the TX datapath.
  • register_fifo : In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI.
RX FIFO mode

low_latency

register_fifo

The following 2 modes are possible:
  • low_latency : This mode adds 2-3 cycles of latency to the RX datapath.
  • register_fifo : In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI.
Enable tx_std_pcfifo_full port On/Off When you turn this option On, the TX Phase compensation FIFO outputs a FIFO full status flag.
Enable tx_std_pcfifo_empty port On/Off When you turn this option On, the TX Phase compensation FIFO outputs a FIFO empty status flag.
Enable rx_std_pcfifo_full port On/Off When you turn this option On, the RX Phase compensation FIFO outputs a FIFO full status flag.
Enable rx_std_pcfifo_empty port On/ Off When you turn this option On, the RX Phase compensation FIFO outputs a FIFO empty status flag.

Byte Ordering Block Parameters

The RX byte ordering block realigns the data coming from the byte deserializer. This block is necessary when the PCS to FPGA fabric interface width is greater than the PCS datapath. Because the timing of the RX PCS reset logic is indeterminate, the byte ordering at the output of the byte deserializer may or may not match the original byte ordering of the transmitted data. The following table describes the byte ordering block parameters.

Parameter Range Description
Enable RX byte ordering On/Off When you turn this option On, the PCS includes the byte ordering block.
Byte ordering control mode

Manual

Auto

Specifies the control mode for the byte ordering block. The following modes are available:
  • Manual : Allows you to control the byte ordering block
  • Auto : The word aligner automatically controls the byte ordering block once word alignment is achieved.
Byte ordering pattern width 8-10 Shows width of the pad that you must specify. This width depends upon the PCS width and whether nor not 8B/10B encoding is used as follows:
Width     8B/10B  Pad Pattern
8/16,32      No      8 bits
10,20,40     No      10 bits
8,16,32      Yes      9 bits
					 
Byte ordering symbol count 1-2 Specifies the number of symbols the word aligner should search for. When the PMA is 16 or 20 bits wide, the byte ordering block can optionally search for 1 or 2 symbols.
Byte order pattern (hex) User-specified 8-10 bit pattern Specifies the search pattern for the byte ordering block.
Byte order pad value (hex) User-specified 8-10 bit pattern Specifies the pad pattern that is inserted by the byte ordering block. This value is inserted when the byte order pattern is recognized.

The byte ordering pattern should occupy the least significant byte (LSB) of the parallel TX data. If the byte ordering block identifies the programmed byte ordering pattern in the most significant byte (MSB) of the byte-deserialized data, it inserts the appropriate number of user-specified pad bytes to push the byte ordering pattern to the LSB position, restoring proper byte ordering.

Enable rx_std_byteorder_ena port On/Off Enables the optional rx_std_byte_order_ena control input port. When this signal is asserted, the byte ordering block initiates a byte ordering operation if the Byte ordering control mode is set to manual. Once byte ordering has occurred, you must deassert and reassert this signal to perform another byte ordering operation. This signal is an synchronous input signal; however, it must be asserted for at least 1 cycle of rx_std_clkout.
Enable rx_std_byteorder_flag port On/Off Enables the optional rx_std_byteorder_flag status output port. When asserted, indicates that the byte ordering block has performed a byte order operation. This signal is asserted on the clock cycle in which byte ordering occurred. This signal is synchronous to the rx_std_clkout clock.

Byte Serializer and Deserializer

The byte serializer and deserializer allow the PCS to operate at twice the data width of the PMA serializer. This feature allows the PCS to run at a lower frequency and accommodate a wider range of FPGA interface widths. The following table describes the byte serialization and deserialization options you can specify.

Table 192.  Byte Serializer and Deserializer Parameters
Parameter Range Description
Enable TX byte serializer On/Off When you turn this option On, the PCS includes a TX byte serializer which allows the PCS to run at a lower clock frequency to accommodate a wider range of FPGA interface widths.
Enable RX byte deserializer On/Off When you turn this option On, the PCS includes an RX byte deserializer and deserializer which allows the PCS to run at a lower clock frequency to accommodate a wider range of FPGA interface widths.

8B/10B

The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. In 8-bit width mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or data word) with proper disparity. The 8B/10B decoder decodes the data into an 8-bit data and 1-bit control identifier. The following table describes the 8B/10B encoder and decoder options.

Table 193.  8B/10B Encoder and Decoder Parameters
Parameter Range Description
Enable TX 8B/10B encoder On/Off When you turn this option On, the PCS includes the 8B/10B encoder.
Enable TX 8B/10B disparity control On/Off When you turn this option On, the PCS includes disparity control for the 8B/10B encoder. Your force the disparity of the 8B/10B encoder using the tx_forcedisp control signal.
Enable RX 8B/10B decoder On/Off When you turn this option On, the PCS includes the 8B/10B decoder.

Rate Match FIFO

The rate match FIFO compensates for the very small frequency differences between the local system clock and the RX recovered clock. The following table describes the rate match FIFO parameters.

Table 194.  Rate Match FIFO Parameters
Parameter Range Description
Enable RX rate match FIFO On/Off When you turn this option On , the PCS includes a FIFO to compensate for the very small frequency differences between the local system clock and the RX recovered clock.
RX rate match insert/delete +ve pattern (hex) User-specified 20 bit pattern Specifies the +ve (positive) disparity value for the RX rate match FIFO as a hexadecimal string.
RX rate match insert/delete -ve pattern (hex) User-specified 20 bit pattern Specifies the -ve (negative) disparity value for the RX rate match FIFO as a hexadecimal string.
Enable rx_std_rm_fifo_empty port On/Off When you turn this option On, the rate match FIFO outputs a FIFO empty status flag. The rate match FIFO compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skip (SKP) symbols or ordered sets from the inter‑packet gap (IPG) or idle stream. This port is only used for XAUI, GigE, and Serial RapidIO in double width mode. In double width mode, the FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
Enable rx_std_rm_fifo_full port On/Off When you turn this option On, the rate match FIFO outputs a FIFO full status flag. This port is only used for XAUI, GigE, and Serial RapidIO in double width mode.

When you enable the simplified data interface and enable the rate match FIFO status ports, the rate match FIFO bits map to the high-order bits of the data bus as listed in the following table. This table uses the following definitions:

  • Basic double width: The Standard PCS protocol mode GUI option is set to basic. The FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
  • SerialTM RapidIO double width: You are implementing the Serial RapidIO protocol. The FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
Note: If you have the auto-negotiation state machine in your transceiver design, please note that the rate match FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets can cause the auto-negotiation link to fail. For more information, visit Intel Knowledge Base Support Solution.
Table 195.  Status Flag Mappings for Simplified Native PHY Interface
Status Condition Protocol Mapping of Status Flags to RX Data Value
Full PHY IP Core for PCI Express (PIPE)

Basic double width

RXD[62:62] = rx_rmfifostatus[1:0], or

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[30:29] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b11 = full
XAUI, GigE, Serial RapidIO double width rx_std_rm_fifo_full 1'b1 = full
All other protocols Depending on the FPGA fabric to PCS interface width either:

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b11 = full
Empty PHY IP Core for PCI Express (PIPE)

Basic double width

RXD[62:62] = rx_rmfifostatus[1:0], or

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[30:29] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

(2'b10) AND (PAD or EDB)

PAD = K23.7 or 9'h1F7

EDB = K30.7 or 9'h1FE

XAUI, GigE, Serial RapidIO double width rx_std_rm_fifo_empty 1'b1 = empty
All other protocols Depending on the FPGA fabric to PCS interface width either:

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

(2'b10) AND (PAD or EDB) 12

PAD = K23.7 or 9'h1F7

EDB = K30.7 or 9'h1FE

Insertion Basic double width

Serial RapidIO double width

RXD[62:62] = rx_rmfifostatus[1:0], or

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[30:29] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b10
All other protocols Depending on the FPGA fabric to PCS interface width either:

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b10
Deletion Basic double width

Serial RapidIO double width

RXD[62:62] = rx_rmfifostatus[1:0], or

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[30:29] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b01
All other protocols Depending on the FPGA fabric to PCS interface width either:

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b01

Word Aligner and Bit-Slip Parameters

The word aligner aligns the data coming from RX PMA deserializer to a given word boundary. When the word aligner operates in bit-slip mode, the word aligner slips a single bit for every rising edge of the bit slip control signal. The following table describes the word aligner and bit-slip parameters.

Table 196.  Word Aligner and Bit-Slip Parameters
Parameter Range Description
Enable TX bit‑slip On/Off When you turn this option On, the PCS includes the bit‑slip function. The outgoing TX data can be slipped by the number of bits specified by the tx_bitslipboundarysel control signal.
Enable tx_std_bitslipboundarysel control input port On/Off When you turn this option On , the PCS includes the optional tx_std_bitslipboundarysel control input port.
RX word aligner mode

bit_slip

sync_sm

manual

Specifies one of the following 3 modes for the word aligner:
  • Bit_slip : You can use bit slip mode to shift the word boundary. For every rising edge of the rx_bitslip signal, the word boundary is shifted by 1 bit. Each bit‑slip removes the earliest received bit from the received data
  • Sync_sm : In synchronous state machine mode, a programmable state machine controls word alignment. You can only use this mode with 8B/10B encoding. The data width at the word aligner can be 10 or 20 bits. When you select this word aligner mode, the synchronous state machine has hysteresis that is compatible with XAUI. However, when you select cpri for the Standard PCS Protocol Mode, this option selects the deterministic latency word aligner mode.
  • Manual : This mode Enables word alignment by asserting the rx_std_wa_patternalign. This is an edge sensitive signal.
RX word aligner pattern length

7, 8, 10

16, 20, 32

Specifies the length of the pattern the word aligner uses for alignment.
RX word aligner pattern (hex) User-specified Specifies the word aligner pattern in hex.
Number of word alignment patterns to achieve sync 1-256 Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock. The default is 3.
Number of invalid words to lose sync 1-256 Specifies the number of invalid data codes or disparity errors that must be received before the word aligner loses synchronization. The default is 3.
Number of valid data words to decrement error count 1-256 Specifies the number of valid data codes that must be received to decrement the error counter. If the word aligner receives enough valid data codes to decrement the error count to 0, the word aligner returns to synchronization lock.
Run length detector word count 0-63 Specifies the maximum number of contiguous 0s or 1s in the data stream before the word aligner reports a run length violation.
Enable rx_std_wa_patternalign port On/Off Enables the optional rx_std_wa_patternalign control input port. A rising edge on this signal causes the word aligner to align the next incoming word alignment pattern when the word aligner is configured in manual mode.
Enable rx_std_wa_a1a2size port On/Off Enables the optional rx_std_wa_a1a2size control input port.
Enable rx_std_wa_bitslipboundarysel port On/Off Enables the optional rx_std_wa_bitslipboundarysel status output port.
Enable rx_std_wa_bitslip port On/Off Enables the optional rx_std_wa_bitslip control input port.
Enable rx_std_wa_runlength_err port On/Off Enables the optional rx_std_wa_runlength_err control input port.

Bit Reversal and Polarity Inversion

These functions allow you to reverse bit order, byte order, and polarity to correct errors and to accommodate different layouts of data. The following table describes these parameters.

Parameter Range Description
Enable TX bit reversal On/Off When you turn this option On, the word aligner reverses TX parallel data before transmitting it to the PMA for serialization. You can only change this static setting using the Transceiver Reconfiguration Controller.
Enable RX bit reversal On/Off When you turn this option On, the rx_st_bitrev_ena port controls bit reversal of the RX parallel data after it passes from the PMA to the PCS.
Enable RX byte reversal On/Off When you turn this option On, the word aligner reverses the byte order before transmitting data. This function allows you to reverse the order of bytes that were erroneously swapped. The PCS can swap the ordering of both 8 and10 bit words.
Enable TX polarity inversion On/Off When you turn this option On, the tx_std_polinv port controls polarity inversion of TX parallel data before transmitting the parallel data to the PMA.
Enable RX polarity inversion On/Off When you turn this option On, asserting rx_std_polinv controls polarity inversion of RX parallel data after PMA transmission.
Enable rx_std_bitrev_ena port On/Off When you turn this option On, asserting rx_std_bitrev_ena control port causes the RX data order to be reversed from the normal order, LSB to MSB, to the opposite, MSB to LSB. This signal is an asynchronous input.
Enable rx_std_byterev_ena port On/Off When you turn this option On, asserting rx_std_byterev_ena input control port causes swaps the order of the individual 8‑ or 10‑bit words received from the PMA.
Enable tx_std_polinv port On/Off When you turn this option On, the tx_std_polinv input is enabled. You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout.
Enable rx_std_polinv port On/Off When you turn this option On, the rx_std_polinv input is enabled. You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout.
Enable tx_std_elecidle port On/Off When you turn this option On, the tx_std_elecidle input port is enabled. When this signal is asserted, it forces the transmitter to electrical idle. This signal is required for the PCI Express protocol.
Enable rx_std_signaldetect port On/Off When you turn this option On, the optional tx_std_signaldetect output port is enabled. This signal is required for the PCI Express protocol. If enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that you specified.

For SATA / SAS applications, enable this port and set the following QSF assignments to the transceiver receiver pin:

  • set_instance_assignment -name XCVR_RX_SD_ENABLE ON
  • set_instance_assignment -name XCVR_RX_SD_THRESHOLD 7
  • set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_OP55V
  • set_instance_assignment -name XCVR_RX_SD_OFF 1
  • set_instance_assignment -name XCVR_RX_SD_ON 2

PRBS Verifier

You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks support the following patterns:

  • Pseudo-random binary sequence (PRBS)
  • Square wave
Table 197.  PRBS Parameters
Parameter Range Description
Enable rx_std_prbs ports On/Off When you turn this option On, the PCS includes the rx_std_prbs_done and rx_std_prbs_err signals to provide status on PRBS operation.
12 PAD and EBD are control characters. PAD character is typically used fo fill in the remaining lanes in a multi-lane link when one of the link goes to logical idle state. EDB indicates End Bad Packet.