V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

4.3. 10GBASE-KR PHY Performance and Resource Utilization

This topic provides performance and resource utilization for the IP core in Arria V GZ and Stratix V devices.

The following table shows the typical expected resource utilization for selected configurations using the current version of the Intel® Quartus® Prime software targeting a Stratix V GT (5SGTMC7K2F40C2) device. The numbers of ALMs and logic registers are rounded up to the nearest 100. Resource utilization numbers reflect changes to the resource utilization reporting starting in the Quartus II software v14.1 release for 28 nm device families and upcoming device families.

Table 24.  10GBASE-KR PHY Performance and Resource Utilization
Module Options ALMs Logic Registers Memory

10GBASE-KR PHY only, no AN or LT

400

700

0

10GBASE-KR PHY with AN and Sequencer

1000

1700

0

10GBASE-KR PHY with LT and Sequencer,

2100

2300

0

10GBASE-KR PHY with AN, LT, and Sequencer

2700

3300

0

10GBASE-KR MIF, Port A depth 256, width 16, ROM (For reconfiguration from low latency or 1GbE mode)

0

0

1 (M20K)

Low Latency MIF, Port A depth 256, width 16, ROM (Required for auto-negotiation and link training.)

0

0

1 (M20K)

10GBASE-KR PHY with FEC

3700

5100

40 (M20K)

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