V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

4.11.2. 10GBASE-KR PHY Control and Status Interfaces

The 10GBASE-KR XGMII and GMII interface signals drive data to and from PHY.
Table 36.  Control and Status Signals
Signal Name Direction Description
rx_block_lock Output Asserted to indicate that the block synchronizer has established synchronization.
rx_hi_ber Output Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10-4.
pll_locked Output When asserted, indicates the TX PLL is locked.
rx_is_lockedtodata Output When asserted, indicates the RX channel is locked to input data.
tx_cal_busy Output When asserted, indicates that the initial TX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. You must hold the channel in reset until calibration completes.
rx_cal_busy Output When asserted, indicates that the initial RX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.
calc_clk_1g Input An independent clock to calculate the latency of the SGMII TX and RX FIFOs. It is only required for when you enable 1588 in 1G mode.

The calc_clk_1g should have a frequency that is not equivalent to 8 ns (125MHz). The accuracy of the PCS latency measurement is limited by the greatest common denominator (GCD) of the RX and TX clock periods (8 ns) and calc_clk_1g. The GCD is 1 ns, if no other higher common factor exists. When the GCD is 1, the accuracy of the measurement is 1 ns. If the period relationship has too small a phase, the phase measurement requires more time than is available. Theoretically, 8.001 ns would provide 1 ps of accuracy. But this phase measurement period requires 1000 cycles to converge which is beyond the averaging capability of the design. The GCD of the clock periods should be no less than 1/64 ns (15ps).

To achieve high accuracy for all speed modes, the recommended frequency for calc_clk_1g is 80 MHz. In addition, the 80 MHz clock should have same parts per million (ppm) as the 125 MHz pll_ref_clk_1g input. The random error without a rate match FIFO mode is:

  • +/- 1 ns at 1000 Mbps
  • +/- 5 ns at 100 Mbps
  • +/- 25 ns at 10 Mbps
rx_sync_status Output When asserted, indicates the Standard PCS word aligner has aligned to in incoming word alignment pattern.
tx_pcfifo_error_1g Output When asserted, indicates that the Standard PCS TX phase compensation FIFO is either full or empty.
rx_pcfifo_error_1g Output When asserted, indicates that the Standard PCS RX phase compensation FIFO is either full or empty.
lcl_rf Input When asserted, indicates a Remote Fault (RF).The MAC to sends this fault signal to its link partner. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword. Bit 3 of the Auto Negotiation Advanced Remote Fault register (0xC2) records this error.
tm_in_trigger[3:0] Input This is an optional signal that can be used for hardware testing by using an oscilloscope or logic analyzer to trigger events. If unused, tie this signal to 1'b0.
tm_out_trigger[3:0] Output This is an optional signal that can be used for hardware testing by using an oscilloscope or logic analyzer to trigger events. You can ignore this signal if not used.
rx_rlv Output When asserted, indicates a run length violation.
rx_clkslip Input When you turn this signal on, the deserializer skips one serial bit or the serial clock is paused for one cycle to achieve word alignment. As a result, the period of the parallel clock can be extended by 1 unit interval (UI). This is an optional control input signal.
rx_latency_adj_1g[21:0] Output When you enable 1588, this signal outputs the real time latency in GMII clock cycles (125 MHz) for the RX PCS and PMA datapath for 1G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 21 represent the number of clock cycles.
tx_latency_adj_1g[21:0] Output When you enable 1588, this signal outputs real time latency in GMII clock cycles (125 MHz) for the TX PCS and PMA datapath for 1G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 21 represent the number of clock cycles.
rx_latency_adj_10g[15:0] Output When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles.
tx_latency_adj_10g[15:0] Output When you enable 1588, this signal outputs real time latency in XGMII clock cycles (156.25 MHz) for the TX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles.
rx_data_ready Output When asserted, indicates that the MAC can begin sending data to the 10GBASE-KR PHY IP Core.
tx_frame Output

Asynchronous status flag output of the TX FEC module. When asserted, indicates the beginning of the generated 2112-bit FEC frame.

rx_clr_counters Input

When asserted, resets the status counters in the RX FEC module. This is an asynchronous input.

rx_frame Output

Asynchronous status flag output of the RX FEC module. When asserted, indicates the beginning of a 2112-bit received FEC frame.

rx_block_lock Output

Asynchronous status flag output of the RX FEC module. When asserted, indicates successful FEC block lock.

rx_parity_good Output

Asynchronous status flag output of the RX FEC module. When asserted, indicates that the parity calculation is good for the current received FEC frame. Used in conjunction with the rx_frame signal.

rx_parity_invalid Output Asynchronous status flag output of the RX FEC module. When asserted, indicates that the parity calculation is not good for the current received FEC frame. Used in conjunction with the rx_frame signal.
rx_error_corrected Output Asynchronous status flag output of the RX FEC module. When asserted, indicates that an error was found and corrected in the current received FEC frame. Used in conjunction with the rx_frame signal.

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