V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

20.5.2.5. XCVR_ANALOG_SETTINGS_PROTOCOL

Pin Planner and Assignment Editor Name

Transceiver Analog Settings Protocol

Description

Specifies the protocol that a transceiver implements. When you use this setting for fully characterized devices, the Intel® Quartus® Prime software automatically sets the optimal values for analog settings, including the VOD, pre-emphasis, and slew rate. For devices that are not fully characterized, the Intel® Quartus® Prime software specifies these settings using preliminary data. If you assign a value to XCVR_ANALOG_SETTINGS_PROTOCOL, you cannot assign a value for any settings that this parameter controls. For example, for PCIe, the XCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XCVR_RX_BYPASS_EQ_STAGES_234. If you also assign a value to this parameter, a Intel® Quartus® Prime Fitter error results as shown in the following example:

Error (21215)

Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" value
on instance "pci_interface_ddf2:u_pci_interface_2|
PCIE_8x8Gb_HARDIP_2:PCIe2_Interface.U_PCIE_CORE|
altpcie_sv_hip_ast_hwtcl:pcie_8x8gb_hardip_2_inst|
altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b
|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:
inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_rx_pma:rx_pma.
sv_rx_pma_inst|rx_pmas[8].rx_pma.rx_pma_buf": Only one QSF
setting for the parameter is allowed.

Options

The following protocol values are defined:
  • BASIC
  • CEI
  • CPRI
  • INTERLAKEN
  • PCIE_GEN1
  • PCIE_GEN2
  • PCIE_GEN3
  • QPI
  • SFIS
  • SONET
  • SRIO
  • TENG_1588
  • TENG_BASER
  • TENG_SDI
  • XAUI

Assign To

Pin - TX and RX serial data

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