V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

9.6. PHY for PCIe (PIPE) Input Data from the PHY MAC

Input data signals are driven from the PHY MAC to the PCS. This interface is compliant to the appropriate PIPE interface specification.

For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Specifications.
Table 112.  Avalon-ST TX Inputs
Signal Name Direction Description
Gen1 and Gen2
pipe_txdata[31:0],[15:0], or [7:0] Input Parallel PCI Express data input bus. For the 16-bit interface, 16 bits represent 2 symbols of transmit data. Bits [7:0] is transmitted first; bits[15:8] are transmitted second. Bit 0 if the first to be transmitted. For the 32-bit interface, 32 bits represent the 4 symbols of TX data. Bits[23:16] are the third symbol to be transmitted and bits [31:24] are the fourth symbol.
pipe_txdatak[(3:0],[1:0] or [0] Input

For Gen1 and Gen2, data and control indicator for the received data. When 0, indicates that pipe_txdata is data, when 1, indicates that pipe_txdata is control.

For Gen3, Bit[0] corresponds to pipe_txdata[7:0], bit[1] corresponds to pipe_txdata[15:8], and so on.

pipe_txcompliance Input Asserted for one cycle to set the running disparity to negative. Used when transmitting the compliance pattern. Refer to section 6.11 of the Intel PHY Interface for PCI Express (PIPE) Architecture for more information.
pipe_tx_data_valid[<n>-1:0] Input

For Gen3, pipe_tx_data_valid[<n>-1:0] is deasserted by the MAC to instruct the PHY to ignore pipe_txdata for one clock cycle. A value of 0 indicates the PHY should use the data. A value of 1 indicates the PHY should not use the data.

tx_blk_start Input For Gen3, specifies start block byte location for TX data in the 128-bit block data. Used when the interface between the PCS and PHY MAC is 32 bits. Not used for the Gen1 and Gen2 data rates.
tx_sync_hdr[1:0] Input

For Gen3, indicates whether the 130-bit block being transmitted is a Data or Control Ordered Set Block. The following encodings are defined:

  • 2'b10: Data block
  • 2'b01: Control Ordered Set Block

This value is read when tx_blk_start = 1b’1. Refer to “Section Lane Level Encoding” in the PCI Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding. Not used for the Gen1 and Gen2 data rates.

pipe_txdetectrx_loopback Input This signal instructs the PHY to start a receive detection operation. After power-up asserting this signal starts a loopback operation. Refer to section 6.4 of the Intel PHY Interface for PCI Express (PIPE) for a timing diagram.
pipe_txelecidle Input This signal forces the transmit output to electrical idle. Refer to section 7.3 of the Intel PHY Interface for PCI Express (PIPE) for timing diagrams.
pipe_powerdown<n>[1:0] Input

This signal requests the PHY to change its power state to the specified state. The following encodings are defined:

  • 2’b00– P0, normal operation
  • 2’b01–P0s, low recovery time latency, power saving state
  • 2’b10–P1, longer recovery time (64 us maximum latency), lower power state
  • 2’b11–P2, lowest power state. (not supported)
pipe_txdeemph Input

Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it selects the transmitter de-emphasis:

  • 1'b0: -6 dB
  • 1'b1: -3.5 dB
pipe_g3_txdeemph[17:0] Input

For Gen3, selects the transmitter de-emphasis. The 18 bits specify the following coefficients:

  • [5:0]: C-1
  • [11:6]: C0
  • [17:12]: C+1

Refer toTable 113 for presets to TX de-emphasis mappings.

In Gen3 capable designs, the TX deemphasis for Gen2 data rates is always -6 dB. The TX deemphasis for Gen1 data rate is always -3.5 dB.

pipe_txmargin[3<n>-1:0] Input

Transmit VOD margin selection. The MAC PHY sets the value for this signal based on the value from the Link Control 2 Register. The following encodings are defined:

  • 3'b000: Normal operating range
  • 3'b001: Full swing: 800 - 1200 mV; Half swing: 400 - 700 mV
  • 3'b010:–3’b011: Reserved
  • 3'b100–3’b111: If last value, full swing: 200 - 400 mV, half swing: 100 - 200 mV else reserved
pipe_txswing Input

Indicates whether the transceiver is using full- or low-swing voltages as defined by the tx_pipemargin.

  • 1’b0–Full swing.
  • 1’b1–Low swing.
pipe_rxpolarity Input When 1, instructs the PHY layer to invert the polarity on the received data. PCIe Gen 1 & 2 has its inversion blocks placed immediately prior to word alignment, whereas PCIe Gen 3 inverts the data coming from the PMA prior to block synchronization.
pipe_rate[1:0] Input

The 2-bit encodings have the following meanings:

  • 2’b00: Gen1 rate (2.5 Gbps)
  • 2’b01: Gen2 rate (5.0 Gbps)
  • 2’b1x: Gen3 (8.0 Gbps)

The Rate Switch from Gen1 to Gen2 Timing Diagram illustrates the timing of a rate switch from Gen1 to Gen2 and back to Gen1.

rx_eidleinfersel[3<n>-1:0] Input

When asserted high, the electrical idle state is inferred instead of being identified using analog circuitry to detect a device at the other end of the link. The following encodings are defined:

  • 3'b0xx: Electrical Idle Inference not required in current LTSSM state
  • 3'b100: Absence of COM/SKP OS in 128 ms window for Gen1 or Gen2
  • 3'b101: Absence of TS1/TS2 OS in 1280 UI interval for Gen1 or Gen2
  • 3'b110: Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2
  • 3'b111: Absence of Electrical Idle exit in 128 ms window for Gen1
pipe_rxpresethint[2:0] Input Provides the RX preset hint for the receiver. Only used for the Gen3 data rate.
Table 113.  Preset Mappings to TX De-Emphasis
Preset C+1 C0 C-1
1 001001 011010 000000
2 000110 011101 000000
3 000111 011100 000000
4 000101 011110 000000
5 000000 100011 000000
6 000000 011111 000100
7 000000 011110 000101
8 000111 011000 000100
9 000101 011010 000100
10 000000 011101 000110
11 001011 011000 000000

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