9.6. PHY for PCIe (PIPE) Input Data from the PHY MAC
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Specifications.
|Gen1 and Gen2|
|pipe_txdata[31:0],[15:0], or [7:0]||Input||Parallel PCI Express data input bus. For the 16-bit interface, 16 bits represent 2 symbols of transmit data. Bits [7:0] is transmitted first; bits[15:8] are transmitted second. Bit 0 if the first to be transmitted. For the 32-bit interface, 32 bits represent the 4 symbols of TX data. Bits[23:16] are the third symbol to be transmitted and bits [31:24] are the fourth symbol.|
|pipe_txdatak[(3:0],[1:0] or ||Input||
For Gen1 and Gen2, data and control indicator for the received data. When 0, indicates that pipe_txdata is data, when 1, indicates that pipe_txdata is control.
For Gen3, Bit corresponds to pipe_txdata[7:0], bit corresponds to pipe_txdata[15:8], and so on.
|pipe_txcompliance||Input||Asserted for one cycle to set the running disparity to negative. Used when transmitting the compliance pattern. Refer to section 6.11 of the Intel PHY Interface for PCI Express (PIPE) Architecture for more information.|
For Gen3, pipe_tx_data_valid[<n>-1:0] is deasserted by the MAC to instruct the PHY to ignore pipe_txdata for one clock cycle. A value of 0 indicates the PHY should use the data. A value of 1 indicates the PHY should not use the data.
|tx_blk_start||Input||For Gen3, specifies start block byte location for TX data in the 128-bit block data. Used when the interface between the PCS and PHY MAC is 32 bits. Not used for the Gen1 and Gen2 data rates.|
For Gen3, indicates whether the 130-bit block being transmitted is a Data or Control Ordered Set Block. The following encodings are defined:
This value is read when tx_blk_start = 1b’1. Refer to “Section 188.8.131.52. Lane Level Encoding” in the PCI Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding. Not used for the Gen1 and Gen2 data rates.
|pipe_txdetectrx_loopback||Input||This signal instructs the PHY to start a receive detection operation. After power-up asserting this signal starts a loopback operation. Refer to section 6.4 of the Intel PHY Interface for PCI Express (PIPE) for a timing diagram.|
|pipe_txelecidle||Input||This signal forces the transmit output to electrical idle. Refer to section 7.3 of the Intel PHY Interface for PCI Express (PIPE) for timing diagrams.|
This signal requests the PHY to change its power state to the specified state. The following encodings are defined:
Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it selects the transmitter de-emphasis:
For Gen3, selects the transmitter de-emphasis. The 18 bits specify the following coefficients:
Refer toTable 113 for presets to TX de-emphasis mappings.
In Gen3 capable designs, the TX deemphasis for Gen2 data rates is always -6 dB. The TX deemphasis for Gen1 data rate is always -3.5 dB.
Transmit VOD margin selection. The MAC PHY sets the value for this signal based on the value from the Link Control 2 Register. The following encodings are defined:
Indicates whether the transceiver is using full- or low-swing voltages as defined by the tx_pipemargin.
|pipe_rxpolarity||Input||When 1, instructs the PHY layer to invert the polarity on the received data. PCIe Gen 1 & 2 has its inversion blocks placed immediately prior to word alignment, whereas PCIe Gen 3 inverts the data coming from the PMA prior to block synchronization.|
The 2-bit encodings have the following meanings:
The Rate Switch from Gen1 to Gen2 Timing Diagram illustrates the timing of a rate switch from Gen1 to Gen2 and back to Gen1.
When asserted high, the electrical idle state is inferred instead of being identified using analog circuitry to detect a device at the other end of the link. The following encodings are defined:
|pipe_rxpresethint[2:0]||Input||Provides the RX preset hint for the receiver. Only used for the Gen3 data rate.|
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