9.6.3. Timing Analysis Description for Stratix 10 EMIF IP
The .sdc file also contains Tool Command Language (.tcl) scripts which perform various timing analyses specific to memory interfaces.
Two timing analysis flows are available for Stratix 10 EMIF IP:
- Early I/O Timing Analysis, which is a precompilation flow.
- Full Timing Analysis, which is a post-compilation flow.
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