External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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10.6.11. Debugging Checklist

The following checklist is a good starting point when debugging an external memory interface.
Table 86.  Checklist



Try a different fit.

Check IP parameters at the operating frequency (tMRD, tWTR for example).

Ensure you have constrained your design with proper timing deration and have closed timing.

Simulate the design. If it fails in simulation, it will fail in hardware.

Analyze timing.

Place and assign RUP and RDN (OCT).

Measure the power distribution network (PDN).

Measure signal integrity.

Measure setup and hold timing.

Measure FPGA voltages.

Vary voltages.

Heat and cool the PCB.

Operate at a lower or higher frequency.

Check board timing and trace Information.

Check LVDS and clock sources, I/O voltages and termination.

Check PLL clock source, specification, and jitter.

Ensure the correct number of PLL phase steps take place during calibration. If the number stated in the IP does not match the number, you may have manually altered the PLL.

Retarget to a smaller interface width or a single bank.