External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.6.1.4.2. Arria II, Arria V, Cyclone V, Stratix IV and Stratix V

Read capture timing analysis indicates the amount of slack on the DDR DQ signals that are latched by the FPGA using the DQS strobe output of the memory device.

Read Capture

The read capture timing paths are analyzed by a combination of the TimeQuest Timing Analyzer using the set_input_delay (max and min), set_max_delay, and set_min_delay constraints, and further steps to account for calibration that occurs at runtime. The UniPHY IP include timing constraints in the <phy_variation_name>.sdc file, and further slack analysis in <phy_variation_name>_report_timing.tcl and <phy_variation_name>_report_timing_core.tcl files.

In Arria II and Stratix IV devices, the margin is reported based on a combination of the TimeQuest Timing Analyzer calculation results and further processing steps that account for the calibration that occurs at runtime. First, the TimeQuest analyzer returns the base setup and hold slacks, and further processing steps adjust the slacks to account for effects which the TimeQuest analyzer cannot model.

Write

Write timing analysis indicates the amount of slack on the DDR DQ signals that are latched by the memory device using the DQS strobe output from the FPGA device. The write timing paths are analyzed by a combination of the TimeQuest Timing Analyzer using the set_output_delay (max and min) and further steps to account for calibration that occurs at runtime. The UniPHY IP includes timing constraints in the <phy_variation_name>.sdc (UniPHY) file, and further slack analysis in the <phy_variation_name>_report_timing.tcl and <phy_variation_name>_report_timing_core.tcl files.

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