External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

2.2.1. Termination for DDR2 SDRAM

DDR2 adheres to the JEDEC standard of governing Stub-Series Terminated Logic (SSTL), JESD8-15a, which includes four different termination schemes.

Two commonly used termination schemes of SSTL are:

  • Single parallel terminated output load with or without series resistors (Class I, as stated in JESD8-15a)
  • Double parallel terminated output load with or without series resistors (Class II, as stated in JESD8-15a)

Depending on the type of signals you choose, you can use either termination scheme. Also, depending on your design’s FPGA and SDRAM memory devices, you may choose external or internal termination schemes.

To reduce system cost and simplify printed circuit board layout, you may choose not to have any parallel termination on the transmission line, and use point‑to‑point connections between the memory interface and the memory. In this case, you may take advantage of internal termination schemes such as on‑chip termination (OCT) on the FPGA side and on-die termination (ODT) on the SDRAM side when it is offered on your chosen device.

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