External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

2.2.1.2. On-Chip Termination

OCT technology is offered on Arria II GX, Arria II GZ, Arria V, Arria 10, Cyclone V, MAX 10, Stratix III, Stratix IV, and Stratix V devices.

The following table summarizes the extent of OCT support for devices earlier than Arria 10. This table provides information about SSTL‑18 standards because SSTL-18 is the supported standard for DDR2 memory interface by Intel® FPGAs.

For Arria II, Stratix III and Stratix IV devices, on-chip series (RS) termination is supported only on output and bidirectional buffers. The value of RS with calibration is calibrated against a 25-ohm resistor for class II and 50-ohm resistor for class I connected to RUP and RDN pins and adjusted to ± 1% of 25-ohm or 50-ohm . On-chip parallel (RT) termination is supported only on inputs and bidirectional buffers. The value of RT is calibrated against 100-ohm connected to the RUP and RDN pins. Calibration occurs at the end of device configuration. Dynamic OCT is supported only on bidirectional I/O buffers.

For Arria V, Cyclone V, and Stratix V devices, RS and RT values are calibrated against the on-board resistor RZQ. If you want 25 or 50 ohm values for your RS and RT, you must connect a 100 ohm resistor with a tolerance of +/-1% to the RZQ pin .

For more information about on-chip termination, refer to the device handbook for the device that you are using.

Table 26.  On-Chip Termination Schemes  

Termination Scheme

SSTL-18

FPGA Device

Arria II GX

Arria II GZ

Arria V

Cyclone  V

MAX 10

Stratix III and Stratix IV

Stratix V  (1)

Column and Row I/O

Column and Row I/O

Column and Row I/O

Column and Row I/O

Column and Row I/O

Column and Row I/O

Column I/O

On-Chip Series Termination without Calibration

Class I

50

50

50

50

50

50

50

Class II

25

25

25

25

25

25

25

On-Chip Series Termination with Calibration

Class I

50

50

50

50

50

50

50

Class II

25

25

25

25

25

25

25

On-Chip Parallel Termination with Calibration

Class I and Class II

50

50

50

50

50

Note to Table:

  1. Row I/O is not available for external memory interfaces in Stratix V devices.

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