External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

6.2.3. Termination Schemes

The following tables list the recommended termination schemes for major QDR II SRAM memory interface signals.

These signals include write data (D), byte write select (BWS), read data (Q), clocks (K, K#, CQ, and CQ#), address and command (WPS and RPS).

Table 49.  Termination Recommendations for Arria II GX Devices 

Signal Type

HSTL 15/18 Standard

 (1)  (2)

FPGA End Discrete Termination

Memory End Termination

K/K# Clocks

Class I R50 CAL

50-ohm Parallel to VTT

Write Data

Class I R50 CAL

50-ohm Parallel to VTT

BWS

Class I R50 CAL

50-ohm Parallel to VTT

Address  (3)  (4)

Class I Max Current

50-ohm Parallel to VTT

WPS, RPS  (3)  (4)

Class I Max Current

50-ohm Parallel to VTT

CQ/CQ#

Class I

50-ohm  Parallel to VTT

ZQ50

CQ/CQ#

×36 emulated  (5)

Class I

50-ohm  Parallel to VTT

ZQ50

Read Data (Q)

Class I

50-ohm  Parallel to VTT

ZQ50

QVLD  (6)

ZQ50

Notes to Table:

  1. R is effective series output impedance.
  2. CAL is calibrated OCT.
  3. For width expansion configuration, the address and control signals are routed to 2 devices. Recommended termination is 50 -ohm parallel to VTT at the trace split of a balanced T or Y routing topology. For 400 MHz burst length 2 configurations where the address signals are double data rate, it is recommended to use a clamshell placement of the two QDR II SRAM components to achieve minimal stub delays and optimum signal integrity. Clamshell placement is when two devices overlay each other by being placed on opposite sides of the PCB.
  4. A Class I 50 -ohm output with calibration output is typically optimal in double load topologies.
  5. For ×36 emulated mode, the recommended termination for the CQ/CQ# signals is a 50 -ohm parallel termination to VTT at the trace split. Intel recommends that you use this termination when ×36 DQ/DQS groups are not supported in the FPGA.
  6. QVLD is not used in the QDR II or QDR II+ SRAM with UniPHY implementations.
Table 50.  Termination Recommendations for Arria V, Stratix III, Stratix IV, and Stratix V Devices

Signal Type

HSTL 15/18 Standard

 (1)  (2)  (3)

FPGA End Discrete Termination

Memory End Termination

K/K# Clocks

DIFF Class I R50 NO CAL

Series 50 -ohm Without Calibration

Write Data

Class I R50 CAL

50 -ohmParallel to VTT

BWS

Class I R50 CAL

50 -ohmParallel to VTT

Address  (4)  (5)

Class I Max Current

50 -ohmParallel to VTT

WPS, RPS  (4)  (5)

Class I Max Current

50 -ohmParallel to VTT

CQ/CQ#

Class I P50 CAL

ZQ50

CQ/CQ# ×36 emulated  (6)

50 -ohm  Parallel to VTT

ZQ50

Read Data (Q)

Class I P50 CAL

ZQ50

QVLD  (7)

Class I P50 CAL

ZQ50

Notes to Table:

  1. R is effective series output impedance.
  2. P is effective parallel input impedance.
  3. CAL is calibrated OCT.
  4. For width expansion configuration, the address and control signals are routed to 2 devices. Recommended termination is 50-ohm parallel to VTT at the trace split of a balanced T or Y routing topology. For 400 MHz burst length 2 configurations where the address signals are double data rate, it is recommended to use a "clam shell" placement of the two QDR II SRAM components to achieve minimal stub delays and optimum signal integrity. "Clam shell" placement is when two devices overlay each other by being placed on opposite sides of the PCB.
  5. The UniPHY default IP setting for this output is Max Current. A Class 1 50-ohm output with calibration output is typically optimal in single load topologies.
  6. For ×36 emulated mode, the recommended termination for the CQ/CQ# signals is a 50-ohm parallel termination to VTT at the trace split. Intel recommends that you use this termination when ×36 DQ/DQS groups are not supported in the FPGA.
  7. QVLD is not used in the QDR II or QDR II+ SRAM Controller with UniPHY implementations.
Note: Intel recommends that you simulate your specific design for your system to ensure good signal integrity.

For a ×36 QDR II SRAM interface that uses an emulated mode of two ×18 DQS groups in the FPGA, there are two CQ/CQ# connections at the FPGA and a single CQ/CQ# output from the QDR II SRAM device. Intel recommends that you use a balanced T topology with the trace split close to the FPGA and a parallel termination at the split, as shown in the following figure.

Figure 59. Emulated ×36 Mode CQ/CQn Termination Topology


For more information about ×36 emulated modes, refer to the “Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II GX, Stratix III, and Stratix IV Devices" section in the Planning Pin and Resources chapter.

Did you find the information on this page useful?

Characters remaining:

Feedback Message