External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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11.2.9. Burst Length

Burst length affects the efficiency of the controller. A burst length of 8 provides more cycles of data transfer, compared to a burst length of 4.

For a half-rate design that has a command latency of 9 half-rate clock cycles, and a CAS latency of 3 memory clock cycles or 1.5 half rate local clock cycles, the efficiency is 9% for burst length of 4, and 16% for burst length of 8.

  • Burst length of 4 (2 memory clock cycles of data transfer or 1 half-rate local clock cycle)

    Efficiency = number of active cycles of data transfer/total number of cycles

    Efficiency = 1/(1 + CAS + command latency) = 1/(1 + 1.5 + 9) = 1/11.5 = 8.6% or approximately 9%

  • Burst length of 8 (4 memory clock cycles of data transfer or 2 half-rate local clock cycles)

    Efficiency = number of active cycles of data transfer/total number of cycles

    Efficiency = 2/(2 + CAS + command latency) = 2/(2 + 1.5 + 9) = 2/12.5 = 16%

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