External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.6. Diagnostics for UniPHY IP

The Diagnostics tab allows you to set parameters for certain diagnostic functions.

The following table describes parameters for simulation.

Table 84.  Simulation Options

Parameter

Description

Simulation Options

Auto-calibration mode

Specifies whether you want to improve simulation performance by reducing calibration. There is no change to the generated RTL. The following autocalibration modes are available:

  • Skip calibration—provides the fastest simulation. It loads the settings calculated from the memory configuration and enters user mode.
  • Quick calibration—calibrates (without centering) one bit per group before entering user mode.
  • Full calibration—calibrates the same as in hardware, and includes all phases, delay sweeps, and centering on every data bit. You can use timing annotated memory models. Be aware that full calibration can take hours or days to complete.

To perform proper PHY simulation, select Quick calibration or Full calibration. For more information, refer to the “Simulation Options” section in the Simulating Memory IP chapter.

For QDR II, QDR II+ SRAM, and RLDRAM II, the Nios II‑based sequencer must be selected to enable the auto calibration modes selection.

Note: This parameter is not available for MAX 10 devices.

Skip memory initialization delays

When you turn on this option, required delays between specific memory initialization commands are skipped to speed up simulation.

Note: This parameter is not available for MAX 10 devices.

Enable verbose memory model output

Turn on this option to display more detailed information about each memory access during simulation.

Note: This parameter is not available for MAX 10 devices.

Enable support for Nios II ModelSim* flow in Eclipse

Initializes the memory interface for use with the Run as Nios II ModelSim* flow with Eclipse.

This parameter is not available for QDR II and QDR II+ SRAM.

Note: This parameter is not available for MAX 10 devices.

Debug Options

Debug level

Specifies the debug level of the memory interface.

Efficiency Monitor and Protocol Checker Settings

Enable the Efficiency Monitor and Protocol Checker on the Controller Avalon Interface

Enables efficiency monitor and protocol checker block on the controller Avalon interface.

This option is not available for QDR II and QDR II+ SRAM, or for the MAX 10 device family, or for Arria V or Cyclone V designs using the Hard Memory Controller.

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