External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.1.4. QDR II and QDR II+ SRAM Controller with UniPHY Interfaces

The following table lists the QDR II and QDR II+ SRAM signals available for each interface in Qsys and provides a description and guidance on how to connect those interfaces.
Table 59.   QDR II and QDR II+ SRAM Controller with UniPHY Interfaces

Signals in Interface

Interface Type

Description/How to Connect

pll_ref_clk interface

pll_ref_clk

Clock input

PLL reference clock input.

global_reset interface

global_reset_n

Reset input

Asynchronous global reset for PLL and all logic in PHY.

soft_reset interface

soft_reset_n

Reset input

Asynchronous reset input. Resets the PHY, but not the PLL that the PHY uses.

afi_reset interface

afi_reset_n

Reset output (PLL master/no sharing)

When the interface is in PLL master or no sharing modes, this interface is an asynchronous reset output of the AFI interface. This interface is asserted when the PLL loses lock or the PHY is reset.

afi_reset_export interface

afi_reset_export_n

Reset output (PLL master/no sharing)

This interface is a copy of the afi_reset interface. It is intended to be connected to PLL sharing slaves.

afi_reset_in interface

afi_reset_n

Reset input (PLL slave)

When the interface is in PLL slave mode, this interface is a reset input that you must connect to the afi_reset_export_n output of an identically configured memory interface in PLL master mode.

afi_clk interface

afi_clk

Clock output (PLL master/no sharing)

This AFI interface clock can be full‑rate or half-rate memory clock frequency based on the memory interface parameterization. When the interface is in PLL master or no sharing modes, this interface is a clock output.

afi_clk_in interface

afi_clk

Clock input (PLL slave)

This AFI interface clock can be full‑rate or half-rate memory clock frequency based on the memory interface parameterization. When the interface is in PLL slave mode, this is a clock input that you must connect to the afi_clk output of an identically configured memory interface in PLL master mode.

afi_half_clk interface

afi_half_clk

Clock output (PLL master/no sharing)

The AFI half clock that is half the frequency of afi_clk.When the interface is in PLL master or no sharing modes, this interface is a clock output.

afi_half_clk_in interface

afi_half_clk

Clock input (PLL slave)

The AFI half clock that is half the frequency of afi_clk.When the interface is in PLL slave mode, you must connect this afi_half_clk input to the afi_half_clk output of an identically configured memory interface in PLL master mode.

memory interface

mem_a

Conduit

Interface signals between the PHY and the memory device.

The sequencer holds mem_doff_n low during initialization to ensure that internal PLL and DLL circuits in the memory device do not lock until clock signals have stabilized.

mem_cqn

mem_bws_n

mem_cq

mem_d

mem_k

mem_k_n

mem_q

mem_wps_n

mem_rps_n

mem_doff_n

avl_r interface

avl_r_read_req

Avalon-MM Slave

Avalon-MM interface between memory interface and user logic for read requests.

avl_r_ready

avl_r_addr

avl_r_size

avl_r_rdata_valid

avl_r_rdata

avl_w interface

avl_w_write_req

Avalon-MM Slave

Avalon-MM interface between memory interface and user logic for write requests.

avl_w_ready

avl_w_addr

avl_w_size

avl_w_wdata

avl_w_be

status interface

local_init_done

Conduit

Memory interface status signals.

local_cal_success

local_cal_fail

oct interface

rup (Stratix III/IV, Arria II GZ, Arria II GX)

Conduit

OCT reference resistor pins for rup/rdn or rzqin.

rdn (Stratix III/IV, Arria II GZ, Arria II GX)

rzq (Stratix V, Arria V, Cyclone V)

pll_sharing interface

pll_mem_clk

Conduit

Interface signals for PLL sharing, to connect PLL masters to PLL slaves. This interface is enabled only when you set PLL sharing mode to master or slave.

pll_write_clk

pll_addr_cmd_clk

pll_locked

pll_avl_clk

pll_config_clk

pll_hr_clk

pll_p2c_read_clk

pll_c2p_write_clk

pll_dr_clk

dll_sharing interface

dll_delayctrl

Conduit

DLL sharing interface for connecting DLL masters to DLL slaves. This interface is enabled only when you set DLL sharing mode to master or slave.

dll_pll_locked

oct_sharing interface

seriesterminationcontrol(Stratix III/IV/V, Arria II GZ, Arria V, Cyclone V)

Conduit

OCT sharing interface for connecting OCT masters to OCT slaves. This interface is enabled only when you set OCT sharing mode to master or slave.

parallelterminationcontrol (Stratix III/IV/V, Arria II GZ, Arria V, Cyclone V)

terminationcontrol (Arria II GX)

Note to Table:

  1. Signals available only in DLL master mode.

Did you find the information on this page useful?

Characters remaining:

Feedback Message