External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

5.6. RLDRAM II and RLDRAM 3 Layout Guidelines

The following table lists the RLDRAM II and RLDRAM 3 general routing layout guidelines. These guidelines apply to Arria V, Arria 10, Stratix V, and Stratix 10 devices.
Table 47.  RLDRAM II and RLDRAM 3 Layout Guidelines

Parameter

Guidelines

General Routing

  • If you must route signals of the same net group on different layers with the same impedance characteristic, simulate your worst case PCB trace tolerances to ascertain actual propagation delay differences. Typical layer to layer trace delay variations are of 15 ps/inch order.
  • Avoid T-junctions greater than 150 ps.
  • Match all signals within a given DQ group with a maximum skew of ±10 ps and route on the same layer.

Clock Routing

  • Route clocks on inner layers with outer-layer run lengths held to under 150 ps.
  • These signals should maintain a 10-mil (0.254 mm) spacing from other nets.
  • Clocks should maintain a length-matching between clock pairs of ±5 ps.
  • Differential clocks should maintain a length-matching between P and N signals of ±2 ps.
  • Space between different clock pairs should be at least three times the space between the traces of a differential pair.

Address and Command Routing

  • To minimize crosstalk, route address, bank address, and command signals on a different layer than the data and data mask signals.
  • Do not route the differential clock signals close to the address signals.
  • Keep the distance from the pin on the RLDRAM II or RLDRAM 3 component to the stub termination resistor (VTT) to less than 50 ps for the address/command signal group.
  • Keep the distance from the pin on the RLDRAM II or RLDRAM 3 component to the fly-by termination resistor (VTT) to less than 100 ps for the address/command signal group.

External Memory Routing Rules

  • Apply the following parallelism rules for the RLDRAM II or RLDRAM 3 data/address/command groups:
    • 4 mils for parallel runs < 0.1 inch (approximately 1× spacing relative to plane distance).
    • 5 mils for parallel runs < 0.5 inch (approximately 1× spacing relative to plane distance).
    • 10 mils for parallel runs between 0.5 and 1.0 inches (approximately 2× spacing relative to plane distance).
    • 15 mils for parallel runs between 1.0 and 3.3 inch (approximately 3× spacing relative to plane distance).

Maximum Trace Length

  • Keep the maximum trace length of all signals from the FPGA to the RLDRAM II or RLDRAM 3 components to 600 ps.

Trace Matching Guidance

The following layout approach is recommended, based on the preceding guidelines:

  1. If the RLDRAM II interface has multiple DQ groups (×18 or ×36 RLDRAM II/RLDRAM 3 component or width expansion configuration), match all the DK/DK# and QK ,QK # clocks as tightly as possible to optimize the timing margins in your design.
  2. Route the DK/DK# write clock and QK/QK# read clock associated with a DQ group on the same PCB layer. Match these clock pairs to within ±5 ps.
  3. Set the DK/DK# or QK/QK# clock as the target trace propagation delay for the associated data and data mask signals.
  4. Route the data and data mask signals for the DQ group ideally on the same layer as the associated QK/QK# and DK/DK# clocks to within ±10 ps skew of the target clock.
  5. Route the CK/CK# clocks and set as the target trace propagation delays for the address/command signal group. Match the CK/CK# clock to within ±50 ps of all the DK/DK# clocks.
  6. Route the address/control signal group (address, bank address, CS, WE, and REF) ideally on the same layer as the CK/CK# clocks, to within ±20 ps skew of the CK/CK# traces.
Note: It is important to match the delays of CK vs. DK, and CK vs. Addr-Cmd as much as possible.

This layout approach provides a good starting point for a design requirement of the highest clock frequency supported for the RLDRAM II and RLDRAM 3 interfaces.

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