External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.11.4. Write Timing

Negative timing margins may be reported for write timing paths if the PLL phase shift used to generate the write data signals is not optimal.

Adjust the PLL phase shift selection on the write clock PLL output using the PLL parameter editor.

Note: Regenerating the UniPHY-based controller overwrites changes made using the PLL parameter editor.

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