External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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9.4.1.9. DK versus CK (RLDRAM II with UniPHY)

In RLDRAM II Controller with UniPHY Intel FPGA IP designs using the Nios® -based sequencer, DK versus CK timing is a calibrated path that details skew margin for the arrival time of the DK clock versus the arrival time of CK/CK# on the memory side.

The PHY IP reports the margin through an equation. For more information, refer to <phy_variation_name> _report_timing_core.tcl.