External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

2.1.4. Dynamic On-Chip Termination in Stratix III and Stratix IV Devices

Stratix III and Stratix IV devices support on-off dynamic series and parallel termination for a bidirectional I/O in all I/O banks. Dynamic OCT is a new feature in Stratix III and Stratix IV FPGA devices.

You enable dynamic parallel termination only when the bidirectional I/O acts as a receiver and disable it when the bidirectional I/O acts as a driver. Similarly, you enable dynamic series termination only when the bidirectional I/O acts as a driver and is disable it when the bidirectional I/O acts as a receiver. The default setting for dynamic OCT is series termination, to save power when the interface is idle—no active reads or writes.

Note: The dynamic control operation of the OCT is separate to the output enable signal for the buffer. UniPHY IP can enable parallel OCT only during read cycles, saving power when the interface is idle.
Figure 17. Dynamic OCT Between Stratix III and Stratix IV FPGA Devices


Dynamic OCT is useful for terminating any high-performance bidirectional path because signal integrity is optimized depending on the direction of the data. In addition, dynamic OCT also eliminates the need for external termination resistors when used with memory devices that support ODT (such as DDR3 SDRAM), thus reducing cost and easing board layout.

However, dynamic OCT in Stratix III and Stratix IV FPGA devices is different from dynamic ODT in DDR3 SDRAM mentioned in previous sections and these features should not be assumed to be identical.

For detailed information about the dynamic OCT feature in the Stratix III FPGA, refer to the Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook.

For detailed information about the dynamic OCT feature in the Stratix IV FPGA, refer to the I/O Features in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.

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