External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.3.3.1. PHY Settings for UniPHY IP

The following table lists the PHY parameters for UniPHY-based EMIF IP.
Table 68.  PHY Parameters

Parameter

Description

General Settings

Speed Grade

Specifies the speed grade of the targeted FPGA device that affects the generated timing constraints and timing reporting.

Generate PHY only

Turn on this option to generate the UniPHY core without a memory controller. When you turn on this option, the AFI interface is exported so that you can easily connect your own memory controller.

Not applicable to RLDRAM 3 UniPHY as no controller support for RLDRAM 3 UniPHY.

Clocks

Memory clock frequency

The frequency of the clock that drives the memory device. Use up to 4 decimal places of precision.

To obtain the maximum supported frequency for your target memory configuration, refer to the External Memory Interface Spec Estimator page on www.altera.com.

Achieved memory clock frequency

The actual frequency the PLL generates to drive the external memory interface (memory clock).

PLL reference clock frequency

The frequency of the input clock that feeds the PLL. Use up to 4 decimal places of precision.

Rate on Avalon-MM interface

The width of data bus on the Avalon-MM interface. Full results in a width of 2× the memory data width. Half results in a width of 4× the memory data width. Quarter results in a width of 8× the memory data width. Use Quarter for memory frequency 533 MHz and above.

To determine the Avalon-MM interface rate selection for other memories, refer to the local interface clock rate for your target device in the External Memory Interface Spec Estimator page on www.altera.com.

Note: MAX 10 devices support only half-rate Avalon-MM interface.

Achieved local clock frequency

The actual frequency the PLL generates to drive the local interface for the memory controller (AFI clock).

Enable AFI half rate clock

Export the afi_half_rate clock which is running half of the AFI clock rate to the top level.

Advanced PHY Settings

Advanced clock phase control

Enables access to clock phases. Default value should suffice for most DIMMs and board layouts, but can be modified if necessary to compensate for larger address and command versus clock skews.

This option is available for DDR, DDR2 and DDR3 SDRAM only.

Note: This parameter is not available for MAX 10 devices.

Additional address and command clock phase

Allows you to increase or decrease the amount of phase shift on the address and command clock. The base phase shift center aligns the address and command clock at the memory device, which may not be the optimal setting under all circumstances. Increasing or decreasing the amount of phase shift can improve timing. The default value is 0 degrees.

In DDR, DDR2, DDR3 SDRAM, and LPDDR2 SDRAM, you can set this value from -360 to 360 degrees. In QDRII/II+ SRAM and RLDRAM II, the available settings are -45, -22.5, 22.5, and 45.

To achieve the optimum setting, adjust the value based on the address and command timing analysis results.

Note: This parameter is not available for MAX 10 devices.

Additional phase for core-to-periphery transfer

Allows you to phase shift the latching clock of the core-to-periphery transfers. By delaying the latch clock, a positive phase shift value improves setup timing for transfers between registers in the core and the half-rate DDIO_OUT blocks in the periphery, respectively. Adjust this setting according to the core timing analysis.

The default value is 0 degrees. You can set this value from -179 to 179 degrees.

Note: This parameter is not available for MAX 10 devices.

Additional CK/CK# phase

Allows you to increase or decrease the amount of phase shift on the CK/CK# clock. The base phase shift center aligns the address and command clock at the memory device, which may not be the optimal setting under all circumstances. Increasing or decreasing the amount of phase shift can improve timing. Increasing or decreasing the phase shift on CK/CK# also impacts the read, write, and leveling transfers, which increasing or decreasing the phase shift on the address and command clocks does not.

To achieve the optimum setting, adjust the value based on the address and command timing analysis results. Ensure that the read, write, and write leveling timings are met after adjusting the clock phase. Adjust this value when there is a core timing failure after adjusting Additional address and command clock phase.

The default value is 0 degrees. You can set this value from -360 to 360 degrees.

This option is available for LPDDR2, DDR, DDR2, and DDR3 SDRAM only.

Note: This parameter is not available for MAX 10 devices.

Supply voltage

The supply voltage and sub-family type of memory.

This option is available for DDR3 SDRAM only.

I/O standard

The I/O standard voltage. Set the I/O standard according to your design’s memory standard.

PLL sharing mode

When you select No sharing, the parameter editor instantiates a PLL block without exporting the PLL signals. When you select Master, the parameter editor instantiates a PLL block and exports the signals. When you select Slave, the parameter editor exposes a PLL interface and you must connect an external PLL master to drive the PLL slave interface signals.

Select No sharing if you are not sharing PLLs, otherwise select Master or Slave.

For more information about resource sharing, refer to “The DLL and PLL Sharing Interface” section in the Functional Description—UniPHY chapter of the External Memory Interface Handbook.

Note: This parameter is not available for MAX 10 devices.

Number of PLL sharing interfaces

This option allows you to specify the number of PLL sharing interfaces to create, facilitating creation of many one-to-one connections in Qsys flow. In Megawizard, you can select one sharing interface and manually connect the master to all the slaves.

This option is enabled when you set PLL sharing mode to Master.

Note: This parameter is not available for MAX 10 devices.

DLL sharing mode

When you select No sharing, the parameter editor instantiates a DLL block without exporting the DLL signals. When you select Master, the parameter editor instantiates a DLL block and exports the signals. When you select Slave, the parameter editor exposes a DLL interface and you must connect an external DLL master to drive the DLL slave signals.

Select No sharing if you are not sharing DLLs, otherwise select Master or Slave.

For more information about resource sharing, refer to “The DLL and PLL Sharing Interface” section in the Functional Description—UniPHY chapter of the External Memory Interface Handbook.

Note: This parameter is not available for MAX 10 devices.

Number of DLL sharing interfaces

This option allows you to specify the number of DLL sharing interfaces to create, facilitating creation of many one-to-one connections in Qsys flow. In Megawizard, you can select one sharing interface and manually connect the master to all the slaves.

This option is enabled when you set PLL sharing mode to Master.

Note: This parameter is not available for MAX 10 devices.

OCT sharing mode

When you select No sharing, the parameter editor instantiates an OCT block without exporting the OCT signals. When you select Master, the parameter editor instantiates an OCT block and exports the signals. When you select Slave, the parameter editor exposes an OCT interface and you must connect an external OCT control block to drive the OCT slave signals.

Select No sharing if you are not sharing OCT blocks, otherwise select Master or Slave.

For more information about resource sharing, refer to “The OCT Sharing Interface” section in the Functional Description—UniPHY chapter of the External Memory Interface Handbook.

Note: This parameter is not available for MAX 10 devices.

Number of OCT sharing interfaces

This option allows you to specify the number of OCT sharing interfaces to create, facilitating creation of many one-to-one connections in Qsys flow. In Megawizard, you can select one sharing interface and manually connect the master to all the slaves.

This option is enabled when you set PLL sharing mode to Master.

Note: This parameter is not available for MAX 10 devices.

Reconfigurable PLL location

When you set the PLL used in the UniPHY memory interface to be reconfigurable at run time, you must specify the location of the PLL. This assignment generates a PLL that can only be placed in the given sides.

Sequencer optimization

Select Performance to enable the Nios II-based sequencer, or Area to enable the RTL-based sequencer.

Intel recommends that you enable the Nios-based sequencer for memory clock frequencies greater than 400 MHz and enable the RTL‑based sequencer if you want to reduce resource utilization.

This option is available for QDRII and QDR II+ SRAM, and RLDRAM II only.

Note: This parameter is not available for MAX 10 devices.

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