External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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7.3.5. Controller Settings for UniPHY IP

Use the Controller Settings tab to apply the controller settings suitable for your design.
Note: This section describes parameters for the High Performance Controller II (HPC II) with advanced features first introduced in version 11.0 for designs generated in version 11.0 or later. Designs created in earlier versions and regenerated in version 11.0 or later do not inherit the new advanced features; for information on parameters for HPC II without the advanced features, refer to the External Memory Interface Handbook for Quartus II version 10.1, available on the Literature: External Memory Interfaces page of www.altera.com.
Table 82.  Controller Settings for LPDDR2/DDR2/DDR3 SDRAM 

Parameter

Description

Avalon Interface

Generate power-of-2 bus widths for SOPC Builder

Rounds down the Avalon-MM side data bus to the nearest power of 2. You must enable this option for Qsys systems.

is option is enabled, the Avalon data buses are truncated to 256 bits wide. One Avalon read-write transaction of 256 bit width maps to four memory beat transactions, each of 72 bits (8 MSB bits are zero, while 64 LSB bits carry useful content). The four memory beats may comprise an entire burst length-of-4 transaction, or part of a burst-length-of-8 transaction.

Generate SOPC Builder compatible resets

This option is not required when using the IP Catalog or Qsys.

Maximum Avalon-MM burst length

Specifies the maximum burst length on the Avalon-MM bus. Affects the AVL_SIZE_WIDTH parameter.

Enable Avalon-MM byte-enable signal

When you turn on this option, the controller adds the byte enable signal (avl_be) for the Avalon-MM bus to control the data mask (mem_dm) pins going to the memory interface. You must also turn on Enable DM pins if you are turning on this option.

When you turn off this option, the byte enable signal (avl_be) is not enabled for the Avalon-MM bus, and by default all bytes are enabled. However, if you turn on Enable DM pins with this option turned off, all write words are written.

Avalon interface address width

The address width on the Avalon-MM interface.

Avalon interface data width

The data width on the Avalon-MM interface.

Low Power Mode

Enable self-refresh controls

Enables the self-refresh signals on the controller top-level design. These controls allow you to control when the memory is placed into self-refresh mode.

Enable Deep Power-Down Controls

Enables the Deep Power-Down signals on the controller top level. These signals control when the memory is placed in Deep Power-Down mode.

This parameter is available only for LPDDR2 SDRAM.

Enable auto-power down

Allows the controller to automatically place the memory into (Precharge) power-down mode after a specified number of idle cycles. Specifies the number of idle cycles after which the controller powers down the memory in the auto-power down cycles parameter.

Auto power-down cycles

The number of idle controller clock cycles after which the controller automatically powers down the memory. The legal range is from 1 to 65,535 controller clock cycles.

Efficiency

Enable user auto refresh controls

Enables the user auto-refresh control signals on the controller top level. These controller signals allow you to control when the controller issues memory autorefresh commands.

Enable auto precharge control

Enables the autoprecharge control on the controller top level. Asserting the autoprecharge control signal while requesting a read or write burst allows you to specify whether the controller should close (autoprecharge) the currently open page at the end of the read or write burst.

Local-to-memory address mapping

Allows you to control the mapping between the address bits on the Avalon‑MM interface and the chip, row, bank, and column bits on the memory.

Select Chip-Row-Bank-Col to improve efficiency with sequential traffic.

Select Chip-Bank-Row-Col to improve efficiency with random traffic.

Select Row-Chip-Bank-Col to improve efficiency with multiple chip select and sequential traffic.

Command queue look ahead depth

Selects a look-ahead depth value to control how many read or writes requests the look-ahead bank management logic examines. Larger numbers are likely to increase the efficiency of the bank management, but at the cost of higher resource usage. Smaller values may be less efficient, but also use fewer resources. The valid range is from 1 to 16.

Enable reordering

Allows the controller to perform command and data reordering that reduces bus turnaround time and row/bank switching time to improve controller efficiency.

Starvation limit for each command

Specifies the number of commands that can be served before a waiting command is served. The valid range is from 1 to 63.

Configuration, Status, and Error Handling

Enable Configuration and Status Register Interface

Enables run-time configuration and status interface for the memory controller. This option adds an additional Avalon-MM slave port to the memory controller top level, which you can use to change or read out the memory timing parameters, memory address sizes, mode register settings and controller status. If Error Detection and Correction Logic is enabled, the same slave port also allows you to control and retrieve the status of this logic.

CSR port host interface

Specifies the type of connection to the CSR port. The port can be exported, internally connected to a JTAG Avalon Master, or both.

Select Internal (JTAG) to connect the CSR port to a JTAG Avalon Master.

Select Avalon-MM Slave to export the CSR port.

Select Shared to export and connect the CSR port to a JTAG Avalon Master.

Enable error detection and correction logic

Enables ECC for single-bit error correction and double-bit error detection. Your memory interface must be a multiple of 16, 24, 40, or 72 bits wide to use ECC.

Enable auto error correction

Allows the controller to perform auto correction when a single-bit error is detected by the ECC logic.

Multiple Port Front End

Export bonding port

Turn on this option to export bonding interface for wider avalon data width with two controllers. Bonding ports are exported to the top level.

Number of ports

Specifies the number of Avalon-MM Slave ports to be exported. The number of ports depends on the width and the type of port you selected. There are four 64-bit read FIFOs and four 64-bit write FIFOs in the multi-port front-end (MPFE) component. For example, If you select 256 bits width and bidirectional slave port, all the FIFOs are fully utilized, therefore you can only select one port.

Note: This parameter is not available for MAX 10 devices.

Width

Specifies the local data width for each Avalon-MM Slave port. The width depends on the type of slave port and also the number of ports selected. This is due to the limitation of the FIFO counts in the MPFE. There are four 64-bit read FIFOs and four 64-bit write FIFOs in the MPFE. For example, if you select one bidirectional slave port, you can select up to 256 bits to utilize all the read and write FIFOs.

As a general guideline to choosing an optimum port width for your half-rate or quarter-rate design, apply the following equation:

port width = 2 x DQ width x Interface width multiplier

where the interface width multiplier is 2 for half-rate interfaces and 4 for quarter-rate interfaces.

Priority

Specifies the absolute priority for each Avalon-MM Slave port. Any transaction from the port with higher priority number will be served before transactions from the port with lower priority number.

Weight

Specifies the relative priority for each Avalon-MM Slave port. When there are two or more ports having the same absolute priority, the transaction from the port with higher (bigger number) relative weight will be served first. You can set the weight from a range of 0 to 32.

Type

Specifies the type of Avalon MM slave port to either a bidirectional port, read only port or write only port.

Table 83.  Controller Settings for QDR II/QDR II+ SRAM and RLDRAM II 

Parameter

Description

Generate power-of-2 data bus widths for SOPC Builder

Rounds down the Avalon-MM side data bus to the nearest power of 2. You must enable this option for Qsys systems.

Generate SOPC Builder compatible resets

This option is not required when using the IP Catalog or Qsys.

Maximum Avalon-MM burst length

Specifies the maximum burst length on the Avalon-MM bus.

Enable Avalon-MM byte-enable signal

When you turn on this option, the controller adds a byte-enable signal (avl_be_w) for the Avalon-MM bus, in which controls the bws_n signal on the memory side to mask bytes during write operations.

When you turn off this option, the avl_be_w signal is not available and the controller will always drive the memory bws_n signal so as to not mask any bytes during write operations.

Avalon interface address width

Specifies the address width on the Avalon-MM interface.

Avalon interface data width

Specifies the data width on the Avalon-MM interface.

Reduce controller latency by

Specifies the number of clock cycles by which to reduce controller latency.

Lower controller latency results in lower resource usage and fMAX while higher latency results in higher resource usage and fMAX,

Enable user refresh

Enables user-controlled refresh. Refresh signals will have priority over read/write requests.

This option is available for RLDRAM II only.

Enable error detection parity

Enables per-byte parity protection.

This option is available for RLDRAM II only

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