External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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3.2.6. Dual-DIMM DDR2 Clock, Address, and Command Termination and Topology

The address and command signals on a DDR2 SDRAM interface are unidirectional signals that the FPGA memory controller drives to the DIMM slots. These signals are always Class-I terminated at the memory end of the line, as shown in the following figure.

Always place DDR2 SDRAM address and command Class-I termination after the last DIMM. The interface can have one or two DIMMs, but never more than two DIMMs total.

Figure 39. Multi DIMM DDR2 Address and Command Termination Topology

In the above figure, observe the following points:

  • Board trace A = 1.9 to 4.5 inches (48 to 115 mm)
  • Board trace B = 0.425 inches (10.795 mm)
  • Board trace C = 0.2 to 0.55 inches (5 to 13 mm)
  • Total of board trace A + B + C = 2.5 to 5 inches (63 to 127 mm)
  • RP = 36 to 56-ohm
  • Length match all address and command signals to +250 mils (+5 mm) or +/– 50 ps of memory clock length at the DIMM.

You may place a compensation capacitor directly before the first DIMM slot 1 to improve signal quality on the address and command signal group. If you fit a capacitor, Intel recommends a value of 24 pF.

For more information, refer to Micron TN47-01.