10.7.2.1.3. Address and Command Timing Margin
If you want to evaluate the address and command timing margin, use the same process as in “Write Timing Margin”, only phase step the address and command PLL output (c6 ac_clk_1x). You can achieve this effect using the debug toolkit or system console.
Refer to the External Memory Interface Debug Toolkit chapter in volume 3 of the External Memory Interface Handbook.
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