External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Public
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9.4. Timing Analysis Description

The following sections describe the timing analysis using the respective FPGA data sheet specifications and the user-specified memory data sheet parameters.
  • Core to core (C2C) transfers have timing constraint created and are timing analyzed by the Timing Analyzer. Core timing does not include user logic timing within core or to and from EMIF block. The UniPHY-based IP provides the constrained clock to the customer logic.
  • Core to periphery (C2P) transfers have timing constraint created and are timing analyzed by the timing analyzer.
  • Periphery to core (P2C) transfers have timing constraint created and are timing analyzed by the timing analyzer.
  • Periphery to periphery (P2P) transfers are modeled entirely by a minimum pulse with violation on the hard block, and have no internal timing arc. In UniPHY-based IP, P2P transfers are reported as part of core timing analysis.

To account for the effects of calibration, the UniPHY-based EMIF IP includes additional scripts that are part of the <phy_variation_name>_report_timing.tcl and <phy_variation_name>_ report_timing_core.tcl files that determine the timing margin after calibration. These scripts use the setup and hold slacks of individual pins to emulate what is occurring during calibration to obtain timing margins that are representative of calibrated PHYs. The effects considered as part of the calibrated timing analysis include improvements in margin because of calibration, and quantization error and calibration uncertainty because of voltage and temperature changes after calibration. The calibration effects do not apply to Stratix III devices.