External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.10.2.1. Write Data Assumptions for Stratix III Devices

For Stratix III devices the following additional write data assumptions are necessary:
  • Differential write clock signals (DQS/DQSn) must be generated using the signal splitter.
  • The write data pins (including the DM pins) must be placed in related DQ pins associated with the chosen DQS pin. The only exception to this rule is for QDRII and QDRII+ ×36 interfaces emulated using two ×18 DQ groups. For such interfaces, all of the write data pins must be placed on the same edge of the device (left, right, top, or bottom). Also, the write clock K/K# pin pair should be placed on one of the DQS/DQSn pin pairs on the same edge.
  • All write clock pins must have similar circuit structure.
    • For DDR2 SDRAM interfaces and DDR3 SDRAM with leveling interfaces, all DQS/DQS# write strobes must be fed by DDIO output registers clocked by the write‑leveling delay chain in the OUTPUT_PHASE_ALIGNMENT block.
    • For DDR and DDR2 SDRAM interfaces, all write clock pins must be fed by DDIO output registers clocked by a global or regional clock network.
  • All write data pins must have similar circuit structure.
    • For DDR3 SDRAM interfaces, all write data pins must be fed by either DDIO output registers clocked by the OUTPUT_PHASE_ALIGNMENT block, VCC, or GND.
    • For DDR and DDR2 SDRAM interfaces, all write data pins must be fed by either DDIO output registers clocked by a global or regional clock network, VCC, or GND.
  • The write clock output must be 72,° 90°, or 108° more than the write data output.
    • For DDR2 SDRAM and DDR3 SDRAM with leveling interfaces, the write‑leveling delay chain in the OUTPUT_PHASE_ALIGNMENT block must implement a phase shift of 72°, 90°, or 108° to center‑align write clock with write data.
    • For DDR and DDR2 SDRAM interfaces, the phase shift of the PLL clock used to clock the write clocks must be 72 to 108° more than the PLL clock used to clock the write data clocks to generated center‑aligned clock and data.
  • The T4 (DDIO_MUX) delay chains must all be set to 3. When differential DQS (using splitter) is used, T4 must be set to 2.
  • The programmable rise and fall delay chain settings for all memory clock pins must be set to 0.

The following table lists I/O standards supported for the write clock and write data signals for each memory type and pin location.

Table 500.  I/O standards

MemoryType

Placement

Legal I/O Standards for DQS

Legal I/O Standards for DQ

DDR3 SDRAM

Row I/O

Differential 1.5-V SSTL Class I

1.5-V SSTL Class I

DDR3 SDRAM

Column I/O

Differential 1.5-V SSTL Class I

Differential 1.5-V SSTL Class II

1.5-V SSTL Class I

1.5-V SSTL Class II

DDR2 SDRAM

Any

SSTL-18 Class I

SSTL-18 Class II

Differential 1.8V SSTL Class I

Differential 1.8V SSTL Class II

SSTL-18 Class I

SSTL-18 Class II

DDR SDRAM

Any

SSTL-2 Class I

SSTL-2 Class II

SSTL-2 Class I

SSTL-2 Class II

QDRII and QDR II + SRAM

Any

HSTL-1.5 Class I

HSTL-1.8 Class I

HSTL-1.5 Class I

HSTL-1.8 Class I

RLDRAM II

Any

HSTL-1.5 Class I

HSTL-1.8 Class I

HSTL-1.5 Class I

HSTL-1.8 Class I

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