8. Simulating Memory IP
- A simulator—The simulator must be any Intel-supported VHDL or Verilog HDL simulator
- A design using one of Intel’s external memory IP
- An example driver (to initiate read and write transactions)
- A testbench and a suitable memory simulation model
The Intel External Memory Interface IP is not compatible with the Qsys Testbench System generation feature. Instead, use the simulation example design of your generated IP as a reference for how to create a simulatable design, completed with a memory interface, a memory model, and a traffic generator.
Memory Simulation Models
There are two types of memory simulation models that you can use:
- Intel-provided generic memory model.
The Quartus® Prime software generates this model together with the example design and this model adheres to all the memory protocol specifications. You can parameterize the generic memory model.
- Vendor-specific memory model.
Memory vendors such as Micron and Samsung provide simulation models for specific memory components that you can download from their websites.
Did you find the information on this page useful?