External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.6.1.8. Write Leveling tDSH/tDSS

In DDR2 SDRAM and DDR3 SDRAM interfaces, write leveling tDSH/tDSS timing details the setup and hold margin for the DQS falling edge with respect to the CK clock at the memory.

The PHY IP reports the margin through an equation. For more information, refer to <phy_variation_name> _report_timing_core.tcl.

Did you find the information on this page useful?

Characters remaining:

Feedback Message